Signal Integrity and High Speed Digital High Speed PCB Design Informational

What is the insertion loss budget for a high speed SerDes channel and how do I allocate it?

Q: How do I reduce via transition loss?

Use back-drilled vias: remove the unused portion of the via (stub) that acts as a resonant cavity. Stub resonance frequency: f_res = c / (4 × stub_length × √Dk). A 60 mil stub on FR-4: f_res ≈ 8.5 GHz (destructive for 25+ Gbps). Back-drilling removes the stub, eliminating the resonance. Alternative: use blind/buried vias or microvias (HDI technology) which inherently have no stubs.

Q: What is the most expensive part of the channel?

The PCB material is typically the largest cost driver. Low-loss laminate (Megtron 6) costs 2-4× more than standard FR-4. Connectors: high-speed connectors cost $1-10 per lane (vs $0.10-0.50 for standard connectors). However: the SerDes transceiver IC itself ($10-100+ per lane for 56/112 Gbps PHY) often exceeds the passive channel cost.

What is the insertion loss budget for a high speed SerDes channel and how do I allocate it? The insertion loss budget defines the maximum total attenuation the SerDes channel can tolerate at the Nyquist frequency while maintaining the required BER: (1) Budget by data rate: 10 Gbps NRZ (Nyquist = 5 GHz): total budget ≈ 15-20 dB. 25 Gbps NRZ (Nyquist = 12.5 GHz): total budget ≈ 25-30 dB. 56 Gbps PAM4 (Nyquist = 14 GHz): total budget ≈ 25-35 dB. 112 Gbps PAM4 (Nyquist = 28 GHz): total budget ≈ 30-40 dB. The budget increases with data rate because the SerDes equalization capability improves with each generation. (2) Loss allocation (example: 25 Gbps NRZ, 28 dB total): TX package (BGA to PCB via): 1-3 dB. TX PCB trace (BGA to connector): 4-8 dB (depends on trace length and material). Connector (board-to-board or backplane): 1-3 dB per mating. Cable or backplane: 5-15 dB (depends on length and material). RX PCB trace: 4-8 dB. RX package: 1-3 dB. Total: 16-40 dB (design to fit within the 28 dB budget). (3) Managing the budget: PCB material: FR-4 (standard): 0.8-1.2 dB/inch at 12.5 GHz. Megtron 6 (mid-tier low-loss): 0.4-0.6 dB/inch. Megtron 7 / I-Tera: 0.3-0.4 dB/inch. A 6-inch trace at 25 Gbps: FR-4: 6 × 1.0 = 6.0 dB. Megtron 6: 6 × 0.5 = 3.0 dB (saves 3 dB of the loss budget). The material choice can make or break the design. Via transitions: each via transition adds 0.5-2 dB (depending on the via design). Connectors: high-speed connectors (Samtec, TE Connectivity, Molex) are specified with insertion loss per mating (typically 0.5-2 dB at Nyquist). (4) Equalization reclaims the eye: the TX FFE, RX CTLE, and RX DFE can compensate for 20-30 dB of channel loss. However: equalization amplifies noise and crosstalk. The net equalization benefit depends on the channel response shape (smooth, monotonic loss is easier to equalize than loss with resonances). The channel loss budget already accounts for equalization capability.

Category: Signal Integrity and High Speed Digital

Updated: April 2026

Product Tie-In: PCB Materials, Connectors, Test Equipment

SerDes Channel Loss Budget

The insertion loss budget is the central design constraint for any high-speed serial link, determining the trade-offs between PCB material, trace length, connector selection, and equalization.

Channel Operating Margin (COM)

(1) For IEEE 802.3ck (100G/lane Ethernet): COM (Channel Operating Margin) is the standard metric, replacing simple insertion loss as the channel quality figure of merit. COM accounts for: insertion loss (frequency-dependent), return loss (reflections), crosstalk (NEXT + FEXT from all aggressors), and SerDes equalization capability. A channel passes if COM ≥ 3 dB (or the specification minimum). COM is calculated using a standardized MATLAB script provided in the IEEE specification. (2) For PCIe Gen 5/6: the specification defines a maximum insertion loss at Nyquist and a minimum eye height/width at the receiver after equalization. The PCIe CEM (Card Electromechanical) specification also defines the connector and slot insertion loss allocation.

Channel Loss Budget

FR-4: 0.8-1.2 dB/inch at 12.5 GHz
Megtron 6: 0.4-0.6 dB/inch (saves ~50%)
Via transition: 0.5-2 dB per transition
Connector: 0.5-2 dB per mating
25 Gbps NRZ: ~28 dB total channel budget

Common Questions

Frequently Asked Questions

When should I switch from FR-4 to low-loss material?

At 10 Gbps NRZ with traces < 6 inches: FR-4 is usually acceptable. At 25 Gbps NRZ: FR-4 may work for short traces (< 3 inches) but low-loss material is recommended for longer traces. At 56+ Gbps PAM4: low-loss material is almost always required. The decision depends on: the total trace length, the number of via transitions, and the connector/cable loss. If the total loss exceeds the budget on FR-4: switch to Megtron 6 or better.

How do I reduce via transition loss?

Use back-drilled vias: remove the unused portion of the via (stub) that acts as a resonant cavity. Stub resonance frequency: f_res = c / (4 × stub_length × √Dk). A 60 mil stub on FR-4: f_res ≈ 8.5 GHz (destructive for 25+ Gbps). Back-drilling removes the stub, eliminating the resonance. Alternative: use blind/buried vias or microvias (HDI technology) which inherently have no stubs.

What is the most expensive part of the channel?

The PCB material is typically the largest cost driver. Low-loss laminate (Megtron 6) costs 2-4× more than standard FR-4. Connectors: high-speed connectors cost $1-10 per lane (vs $0.10-0.50 for standard connectors). However: the SerDes transceiver IC itself ($10-100+ per lane for 56/112 Gbps PHY) often exceeds the passive channel cost.

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