What is the effect of fiber weave on skew in a differential pair at high data rates?
Fiber Weave Skew
Fiber weave skew is one of the most subtle and easily overlooked signal integrity issues, becoming significant at data rates above 25 Gbps.
Practical Design Rules
(1) For 10 Gbps and below: fiber weave skew is typically negligible. Standard glass styles (1080, 2116) are acceptable. (2) For 25 Gbps: use spread glass or route at an angle to the weave. Maximum acceptable intra-pair skew: 5-8 ps. (3) For 56-112 Gbps: spread glass is mandatory. Maximum acceptable intra-pair skew: 2-3 ps. Some designs use NE glass (no fiber weave variation) for the most critical layers. (4) Measurement: intra-pair skew can be measured with a TDR (Time Domain Reflectometry) or by measuring the differential-to-common mode conversion (Sdc21) on a VNA. High Sdc21 at a specific frequency indicates skew-induced mode conversion.
Dk variation: ±5-10% (standard), ±2% (spread)
Skew: 5-15 ps over 6 inches (worst case)
25 Gbps: 10 ps = 25% of UI (significant)
Fix: spread glass, angled routing, NE glass
Frequently Asked Questions
How do I specify spread glass to the PCB fabricator?
Include in your fabrication notes: "Signal layers shall use spread glass weave (e.g., 2116-spread or 1078-spread) to minimize fiber weave Dk variation." The fabricator will confirm availability and any cost premium. Some fabricators offer "homogeneous glass" or "flat glass" as their term for spread weave. Always confirm the specific glass style with your fabricator.
Can I simulate fiber weave effects?
Full-wave 3D simulation of fiber weave is possible but computationally expensive (modeling individual glass bundles requires very fine mesh). More practical: use a statistical model with the known Dk variation range and estimate the worst-case skew. Many SI engineers treat fiber weave as a ±X ps skew contribution in the total skew budget without detailed simulation.
Does fiber weave affect single-ended signals?
For single-ended signals: fiber weave causes a small propagation delay variation between different traces. This contributes to trace-to-trace skew in parallel buses (e.g., DDR memory). For SerDes (differential): the intra-pair skew is the primary concern. For matched-length buses: inter-trace skew due to fiber weave adds to the total bus skew budget.