Signal Integrity and High Speed Digital High Speed PCB Design Informational

How do I design the via transition for a high speed differential pair to minimize reflection?

Q: When is back-drilling necessary?

Above 10 Gbps: back-drilling is recommended for PTH vias with stubs > 20 mil. Above 25 Gbps: back-drilling is almost always required. Above 56 Gbps: either back-drilling with tight tolerances (±3 mil) or blind/microvia construction. Cost: back-drilling adds $2-5 per board (modest compared to material cost).

How do I design the via transition for a high speed differential pair to minimize reflection? The via transition is one of the largest impedance discontinuities in a high-speed PCB channel, and minimizing its reflection is critical for signal integrity at data rates above 10 Gbps: (1) Via structure: a plated through-hole (PTH) via is a metal cylinder passing through all layers of the PCB. The via has: a pad on each layer it connects (typically 20-30 mil diameter), an anti-pad (clearance hole) in each ground plane, and a stub (the unused portion of the via below the target layer). Each of these features affects the impedance and creates reflections. (2) Via impedance: a typical PTH via has an impedance of 30-40 ohms (lower than the 50 ohm traces). This impedance mismatch creates a reflection at each via transition. The reflection coefficient: Γ = (Z_via - Z₀)/(Z_via + Z₀) = (35-50)/(35+50) = -0.18 → S11 = -15 dB. At 25 Gbps: this -15 dB reflection is significant and must be improved. (3) Optimization techniques: anti-pad tuning: increase the anti-pad diameter to increase the via impedance toward 50 ohms. Standard anti-pad: 30 mil → via Z ≈ 35 ohm. Enlarged anti-pad: 45-55 mil → via Z ≈ 45-50 ohm. Caution: too large an anti-pad weakens the ground plane and increases via-to-via crosstalk. Back-drilling: remove the via stub (the portion below the target layer). The stub acts as a resonant quarter-wave open stub: f_res = c / (4 × L_stub × √Dk). A 60 mil stub on FR-4: f_res ≈ 8 GHz (destructive for 25+ Gbps). Back-drilling removes the stub, eliminating the resonance. Typical back-drill accuracy: ±4-6 mil. Ground vias: add ground vias (return vias) adjacent to the signal vias. These provide a low-impedance return path for the signal current as it transitions between layers. Without return vias: the return current must find its way through the ground plane capacitance, causing inductance and ringing. Rule: place at least 2 ground vias within 20 mil of each signal via. (4) HDI alternatives: blind vias: via only passes through the layers it connects (no stub). Microvias (HDI): laser-drilled, 4-6 mil diameter, connects only adjacent layers. Lowest parasitic impedance and no stub. Required for 56+ Gbps PAM4 on dense BGAs.

Category: Signal Integrity and High Speed Digital

Updated: April 2026

Product Tie-In: PCB Materials, Connectors, Test Equipment

Via Transition Design

The via transition is the single most common cause of impedance mismatch in high-speed PCB designs, and its optimization is one of the highest-impact activities for signal integrity improvement.

Via Simulation

(1) 3D EM simulation (HFSS, CST, Clarity 3D) is the standard method for optimizing via transitions. The simulation captures the full 3D electromagnetic behavior: pad/anti-pad interaction, stub resonance, and coupling between adjacent vias. Model the complete via field (signal vias + ground vias) and all layers. (2) Parameterize the design: sweep anti-pad size, ground via placement, and stub length. Optimize for minimum S11 and maximum S21 at the target frequency. A well-optimized via can achieve S11 < -25 dB at 14 GHz (56 Gbps PAM4 Nyquist), compared to -15 dB for an unoptimized via. (3) The via is typically the dominant reflection in the channel. Fixing the via often provides more benefit than upgrading the PCB material.

Via Optimization

Via Z: 30-40 ohm (typical PTH) vs 50 ohm trace
Stub resonance: f = c/(4 × L_stub × √Dk)
60 mil stub on FR-4: f_res ≈ 8 GHz
Anti-pad: 45-55 mil → Z_via ≈ 45-50 ohm
Return vias: ≥ 2 ground vias within 20 mil

Common Questions

Frequently Asked Questions

When is back-drilling necessary?

Above 10 Gbps: back-drilling is recommended for PTH vias with stubs > 20 mil. Above 25 Gbps: back-drilling is almost always required. Above 56 Gbps: either back-drilling with tight tolerances (±3 mil) or blind/microvia construction. Cost: back-drilling adds $2-5 per board (modest compared to material cost).

Can I avoid vias entirely?

For short links on the same layer: yes (no layer transition needed). For complex designs with BGA packages: vias are unavoidable (BGA escape routing requires layer transitions). For the most critical links: minimize the number of via transitions (each transition adds 0.5-2 dB of loss and reflection). One via transition per end (TX and RX) is the minimum.

What about via-in-pad?

Via-in-pad: the via is placed directly in the component pad (instead of a dog-bone trace leading to a via). Advantages: shorter trace length, lower parasitic inductance, smaller footprint. Required for: fine-pitch BGAs (< 0.65 mm pitch). The via must be filled and planarized (copper-filled via) for reliable soldering. Cost: copper-filled via-in-pad adds $3-10 per board.

Keep Reading