How do I calculate the impedance of a differential pair on a PCB at multi-GHz data rates?
Differential Pair Impedance
Precise impedance control is the foundation of high-speed PCB design, and even small impedance variations cause reflections that degrade signal integrity.
Frequently Asked Questions
Why 100 ohm differential?
100 ohm was selected as the standard because: it provides a good balance between trace width and spacing (neither too narrow nor too wide). It matches the characteristic impedance of most high-speed I/O driver circuits. 50 ohm single-ended × 2 = 100 ohm (simplifies impedance matching). Nearly all modern SerDes standards (PCIe 5.0/6.0, USB4, 400G Ethernet, DDR5) specify 100 ohm differential impedance.
How does spacing affect differential impedance?
Tighter spacing (smaller S): increases coupling (higher k), reduces Z_diff. Example: S = 5 mil → Z_diff = 100 ohm. S = 15 mil → Z_diff ≈ 96 ohm. This is counter-intuitive: wider spacing makes the two traces behave more like independent 50 ohm lines (Z_diff → 100 ohm), while tight spacing couples them (Z_diff < 100 ohm). For heavily coupled pairs: the common-mode impedance also changes, affecting common-mode noise rejection.
Do I need a 2D field solver?
For data rates below 5 Gbps: approximate formulas (Johnson, Wadell, or IPC-2141 equations) are adequate. Above 5 Gbps: a 2D field solver is recommended (accounts for conductor shape, etch factor, solder mask effect). Above 25 Gbps: a 3D field solver may be needed for discontinuities (via transitions, BGA breakout) that the 2D solver cannot model.