Signal Integrity and High Speed Digital High Speed PCB Design Informational

What is the effect of the anti-pad size on the impedance of a via in a high speed channel?

What is the effect of the anti-pad size on the impedance of a via in a high speed channel? The anti-pad is the clearance hole in each ground plane through which the via passes, and its size directly controls the capacitance and impedance of the via: (1) Via impedance model: the via acts as a coaxial transmission line: the via barrel is the center conductor, and the anti-pad edge (ground plane opening) is the outer conductor. The characteristic impedance: Z_via ≈ (60 / √Dk) × ln(D_antipad / D_drill). Where D_antipad is the anti-pad diameter and D_drill is the drill hole diameter. Smaller anti-pad → more capacitance → lower Z_via. Larger anti-pad → less capacitance → higher Z_via. (2) Typical values: standard anti-pad = 30 mil, drill = 12 mil, FR-4 (Dk=4): Z_via ≈ (60/2) × ln(30/12) = 30 × 0.916 = 27.5 ohm. This is well below the 50 ohm target, causing a reflection. Enlarged anti-pad = 50 mil: Z_via ≈ 30 × ln(50/12) = 30 × 1.427 = 42.8 ohm. Still below 50 ohm but much better. Anti-pad = 72 mil: Z_via ≈ 30 × ln(72/12) = 30 × 1.792 = 53.8 ohm ≈ 50 ohm target. (3) However, the anti-pad size has trade-offs: larger anti-pad weakens the ground plane (removes copper, reduces ground plane continuity). Larger anti-pad increases via-to-via coupling (less shielding between adjacent vias). Very large anti-pads can cause signal integrity issues for other signals routed near the via. (4) Optimization: the optimal anti-pad size is the one that brings Z_via closest to 50 ohm without excessively weakening the ground plane. Use 3D EM simulation to find the optimal size for your specific stackup. For differential vias: the anti-pad affects both the single-ended and differential (odd-mode) impedance. Separate anti-pads per via are often used (each via has its own clearance). Alternatively: an oval or "racetrack" anti-pad (one clearance hole for both vias of the differential pair) can be tuned for the differential impedance.
Category: Signal Integrity and High Speed Digital
Updated: April 2026
Product Tie-In: PCB Materials, Connectors, Test Equipment

Anti-Pad Via Impedance

The anti-pad is one of the simplest and most effective tuning parameters for via impedance matching, yet it is often left at the default size in many designs.

  1. Performance verification: confirm specifications against the application requirements before finalizing the design
  2. Environmental factors: temperature range, humidity, and vibration affect long-term reliability and parameter drift
  3. Cost vs. performance: evaluate whether the application demands premium components or standard commercial grades
  4. Interface compatibility: verify impedance, connector type, and mechanical form factor match the system architecture
  5. Margin allocation: include sufficient design margin to account for manufacturing tolerances and aging effects
Common Questions

Frequently Asked Questions

Should I use the same anti-pad on all layers?

For simplicity: yes, use a uniform anti-pad on all layers (most common practice). For optimization: use a larger anti-pad on the layers where the impedance is most critical (near the signal layer transitions) and a smaller anti-pad on distant layers (to maintain ground plane integrity). This non-uniform approach requires more design effort and manufacturing coordination.

What about non-circular anti-pads?

Oval or racetrack anti-pads: align the long axis with the differential pair direction. This provides a larger clearance between the via and the ground plane in the pair direction (increasing Z_via) while keeping the clearance smaller in the perpendicular direction (maintaining ground plane integrity). This is a common technique for optimizing differential via impedance.

How do I coordinate anti-pad size with the PCB fabricator?

Include the anti-pad size in the Gerber/ODB++ files for each layer. Communicate the required anti-pad size explicitly in the fabrication notes. Many fabricators have default anti-pad rules; make sure your custom size overrides the default. Verify by requesting a cross-section sample of the first production run (the fabricator cuts a via and measures the anti-pad under a microscope).

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