Signal Integrity and High Speed Digital High Speed PCB Design Informational

What is return loss and how does it affect the bit error rate of a high speed serial link?

Q: What is the minimum acceptable return loss?

Rule of thumb: S11 90% of the signal power passes through each discontinuity. For PAM4 at 56+ Gbps: tighter requirements (S11 < -12 to -15 dB) due to the smaller eye opening.

Q: How do I improve the return loss of a connector?

Select a connector with a specified S11 better than your requirement. The connector vendor provides S-parameter models (Touchstone files) for simulation. Add a matching pad or anti-pad optimization at the connector footprint. Use staggered pin assignment (signal pins adjacent to ground pins) for better impedance control. The connector is often the most difficult component to improve (it is a purchased part with fixed geometry).

Q: Can equalization compensate for poor return loss?

Partially. The RX CTLE and DFE can partially compensate for reflections by treating them as additional ISI taps. However: reflections that arrive with long delays (from far-away discontinuities) are harder to equalize (the DFE has a finite number of taps). Equalization does NOT remove the reflected energy; it re-shapes the receiver decision to account for it. Prevention (good impedance design) is always better than compensation (equalization).

What is return loss and how does it affect the bit error rate (BER) of a high speed serial link? Return loss measures the fraction of signal energy reflected back toward the transmitter at any impedance discontinuity, and it directly degrades the received signal quality: (1) Return loss definition: return loss (RL) = -20 × log₁₀(|Γ|) dB. Where Γ = (Z - Z₀)/(Z + Z₀) is the reflection coefficient. Higher RL (more negative S11 dB) = better match = less reflection. RL = 20 dB → 1% of power reflected. RL = 10 dB → 10% of power reflected. RL = 6 dB → 25% of power reflected. (2) Effect on BER: reflections create delayed copies of the signal that arrive at the receiver with the direct signal. These ghost copies: interfere constructively or destructively with the desired signal, reducing the eye opening. Cause inter-symbol interference (ISI) if the reflection delay is comparable to the bit period. Add deterministic jitter (DJ) by shifting the zero-crossing timing. The BER impact depends on: the reflection magnitude (S11 level), the reflection delay (related to the physical distance between the discontinuity and the receiver), and the number of reflections (each impedance discontinuity creates its own reflection). (3) Specification requirements: PCIe Gen5 (32 Gbps): S11 < -10 dB at Nyquist (16 GHz). USB4 Gen3 (20 Gbps): S11 < -12 dB at 10 GHz. IEEE 802.3ck (100G Ethernet): S11 < -8 to -12 dB (depending on channel segment). 5G FR2 antenna feed: S11 < -10 to -15 dB. These specifications ensure that the reflected energy does not significantly degrade the eye at the target BER (typically 10⁻¹²). (4) Multiple reflections: in a real channel with multiple discontinuities (vias, connectors, package): reflections bounce back and forth between discontinuities (multiple-bounce reflections). The total reflected energy is the vector sum of all single and multiple-bounce reflections. In a well-designed channel: the reflections are small enough that multiple-bounce effects are negligible. In a poorly designed channel: multiple-bounce reflections can cause resonant dips in S21 at specific frequencies (notches in the insertion loss), which are very destructive to the eye.

Category: Signal Integrity and High Speed Digital

Updated: April 2026

Product Tie-In: PCB Materials, Connectors, Test Equipment

Return Loss and BER

Return loss management is one of the primary design tasks for high-speed channels, and every impedance discontinuity must be analyzed and optimized.

Parameter	Option A	Option B	Option C
Performance	High	Medium	Low
Cost	High	Low	Medium
Complexity	High	Low	Medium
Bandwidth	Narrow	Wide	Moderate
Typical Use	Lab/military	Consumer	Industrial

Sampling and Quantization

(1) For a 25 Gbps NRZ channel: specification: S11 < -10 to -12 dB at 12.5 GHz. Budget allocation: PCB trace mismatch (±7% impedance tolerance): S11 ≈ -26 dB. Via transition: S11 ≈ -15 to -25 dB (depending on optimization). Connector: S11 ≈ -15 to -20 dB (specified by the connector vendor). Package (BGA): S11 ≈ -15 to -20 dB. The total S11 is the vector sum of all contributions (can add constructively at some frequencies). If multiple discontinuities have S11 ≈ -18 dB each: at some frequency, the vector sum could exceed -10 dB (approaching the specification limit). (2) Time-domain analysis: convert S11 to TDR (time-domain reflectometry) to visualize the impedance profile along the channel. Each reflection appears as a peak or valley in the TDR trace. The TDR amplitude directly corresponds to the impedance: Z(t) = Z₀ × (1 + Γ(t)) / (1 - Γ(t)). This visualization helps identify the specific location of each mismatch.

Performance verification: confirm specifications against the application requirements before finalizing the design
Environmental factors: temperature range, humidity, and vibration affect long-term reliability and parameter drift
Cost vs. performance: evaluate whether the application demands premium components or standard commercial grades

Dynamic Range Considerations

When evaluating return loss and how does it affect the bit error rate of a high speed serial link?, engineers must account for the specific requirements of their target application. The optimal choice depends on the frequency range, power level, environmental conditions, and cost constraints of the overall system design.

Common Questions

Frequently Asked Questions

What is the minimum acceptable return loss?

Rule of thumb: S11 < -10 dB at all frequencies up to the Nyquist frequency. This ensures > 90% of the signal power passes through each discontinuity. For PAM4 at 56+ Gbps: tighter requirements (S11 < -12 to -15 dB) due to the smaller eye opening.

How do I improve the return loss of a connector?

Select a connector with a specified S11 better than your requirement. The connector vendor provides S-parameter models (Touchstone files) for simulation. Add a matching pad or anti-pad optimization at the connector footprint. Use staggered pin assignment (signal pins adjacent to ground pins) for better impedance control. The connector is often the most difficult component to improve (it is a purchased part with fixed geometry).

Can equalization compensate for poor return loss?

Partially. The RX CTLE and DFE can partially compensate for reflections by treating them as additional ISI taps. However: reflections that arrive with long delays (from far-away discontinuities) are harder to equalize (the DFE has a finite number of taps). Equalization does NOT remove the reflected energy; it re-shapes the receiver decision to account for it. Prevention (good impedance design) is always better than compensation (equalization).

Keep Reading