How do I design a split ground plane on a PCB without creating EMI problems?
Split Ground Design Rules
The split ground is a legacy technique that is occasionally necessary but must be implemented with extreme care to avoid creating more problems than it solves.
Frequently Asked Questions
If splits are bad, why do some datasheets show them?
Many older application notes and datasheets (pre-2005) show split-ground layouts because: (1) that was the best practice at the time (2-layer boards without dedicated ground planes). (2) The application note was written for a specific IC and a simple circuit, where the split was easy to manage. The advice does not scale to complex mixed-signal boards. Modern application notes from ADI, TI, and Maxim now recommend unified ground planes. If you see a split-ground recommendation in a datasheet: check the date of the application note and look for updated guidance. Most manufacturers have revised their recommendations.
How do I handle the ADC clock line in a split-ground design?
The ADC clock is a high-speed digital signal that must reach the ADC (which sits at the bridge between the analog and digital grounds). Route the clock on the digital ground side up to the bridge point (the ADC). The clock return current stays on the digital ground. At the ADC: the clock enters the digital pins, and the ADC internally routes it to drive the sampling circuit. The analog sampling noise is handled by the ADC internal design. Do NOT route the clock on the analog ground side (this would inject digital noise into the analog ground). The clock trace should not cross the split at any point other than through the ADC IC.
Can I use stitching capacitors across the split?
Yes. Placing capacitors across the split gap provides a low-impedance path at high frequencies while maintaining DC isolation. Use 100 pF to 10 nF ceramic capacitors (COG type) placed along the split gap at 10-20 mm intervals. The capacitors short the two ground regions together at RF (> 10 MHz), providing a return path for high-frequency signals. At DC and low frequencies: the capacitors are open circuits, maintaining the DC isolation of the split. This technique provides many of the benefits of a unified ground at RF while maintaining the DC separation of the split. It is the recommended approach when a split is mandated by safety or isolation requirements.