How do I route high speed digital signals near RF circuits without causing interference?

Digital-RF Routing Isolation

High-speed digital signals are broadband noise sources: a 100 MHz clock has significant spectral content at 300, 500, 700, and 900 MHz (odd harmonics of the fundamental). These harmonics fall directly into common RF operating bands (cellular, GPS, Wi-Fi, Bluetooth).

Clock Signal Management

(1) The clock is the #1 EMI source on most digital PCBs. The clock signal has the highest harmonic content because it has the fastest edges and the highest repetition rate. A 100 MHz clock with 1 ns edges: spectral content extends to approximately 1/(pi×t_rise) = 318 MHz (significant energy). Harmonics: 300, 500, 700, 900 MHz, etc. At 900 MHz: within the cellular band. (2) Routing rules for clocks near RF: route clock traces on stripline (between two ground planes) for maximum containment. Use the shortest possible trace length (place the clock source next to the destination IC). Add series termination (a resistor matching the source impedance) at the clock source to reduce reflections and ringing. Spread-spectrum clocking (SSCG): modulates the clock frequency by ±0.5-1%, spreading the harmonic energy over a wider bandwidth. This reduces the peak harmonic amplitude by 10-20 dB without affecting digital circuit operation. (3) Differential clocking: use differential clock signals (LVDS, LVPECL) for high-speed digital buses. The differential pair radiates much less than a single-ended signal (the fields from the two conductors partially cancel). The remaining radiation (common-mode) depends on the pair balance: a well-balanced pair radiates 20-30 dB less than a single-ended trace carrying the same signal.

Via Transitions

(1) When a signal transitions between layers through a via: the return current must also transition. If the return current plane changes (e.g., the signal moves from a layer referenced to L2 GND to a layer referenced to L5 GND): the return current must find a path between L2 and L5. Without stitching vias near the signal via: the return current detours to the nearest via connecting L2 and L5. This detour creates a radiating loop. Rule: place ground stitching vias within 1 mm of every signal via that changes reference plane. Multiple stitching vias (2-4) provide the lowest impedance transition. (2) For RF signal vias: add a ring of ground vias around the RF signal via (via fence). This creates a coaxial-like transition through the layer stack, maintaining controlled impedance and minimizing radiation. Typical arrangement: 4-6 ground vias in a ring with 0.5-1 mm radius around the signal via.

Practical Design Review Checklist

(1) Identify all high-speed digital signals (clock, data bus, control signals with edges < 2 ns). (2) Check the routing of each: none should be parallel to RF traces on adjacent layers. All should have a ground plane directly below (or above). None should cross a ground plane gap or split. (3) Check the RF signal routing: the LNA input trace should have no digital traces within 10H on the same layer or any traces on the layer directly below (except the ground plane). The VCO control line should be shielded with ground vias and separated from all digital and switching signals. (4) Verify decoupling: every digital IC has a 100 nF cap within 2 mm of each VCC pin. Every RF IC has 100 pF + 10 nF at each supply pin. (5) Check via transitions: every signal via that changes reference plane has stitching vias within 1 mm. RF signal vias have ground via fences.

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