EMI, EMC, and Shielding PCB EMC Design Informational

What is the correct grounding strategy for a mixed signal PCB with RF, analog, and digital circuits?

Q: My ADC datasheet says to use separate AGND and DGND. Does this mean split the ground?

No. The separate AGND and DGND pins are for internal die bonding purposes and to help with PCB component placement, NOT for split ground planes. Connect both AGND and DGND to the same solid ground plane. The IC is designed so that the analog return current flows through the AGND pins and the digital return current flows through the DGND pins. On the external ground plane: these currents naturally separate (the analog return stays near the analog pins, the digital return stays near the digital pins). If you split the ground and connect AGND to one region and DGND to another: the return current inside the IC must cross from one ground to the other, creating noise coupling within the IC. This degrades the ADC performance (higher noise, lower ENOB, more spurs).

Q: When might I actually want a split ground?

The only scenario where a split ground may be beneficial: a PCB with a very high-power transmitter (> 10 W) and a very sensitive receiver (< -100 dBm) on the same board. The TX output current (amps) flows through the shared ground plane, creating voltage drops that couple into the receiver. In this case: separate ground regions connected at a single star point may reduce the coupling. But: all signal traces between the regions must cross through the star point. No traces may cross the split gap. This is complex to design and should only be attempted if the unified ground approach has been proven insufficient through measurement. For ALL other cases (99%+ of mixed-signal designs): use a unified ground.

Q: Does the ground plane need to extend beyond the board edge?

The ground plane should extend to the board edge (no copper pullback required on ground layers for most fabricators). The ground plane at the board edge provides: a ground return path for edge-routed traces, a ground connection for perimeter-mounted connectors, and a ground for the shield can perimeter vias. Some fabricators require a small copper pullback from the board edge (0.2-0.5 mm) to prevent copper burrs during routing. This pullback is acceptable and does not significantly affect the ground plane performance. For critical EMI performance: extend the ground plane to the edge and specify the minimum pullback allowed by the fabricator.

The correct grounding strategy for a mixed-signal PCB with RF, analog, and digital circuits is a unified, solid ground plane: (1) Single ground plane: use one continuous copper ground plane layer (typically L2 in a 4+ layer stack-up) as the return path for ALL circuits: RF, analog, and digital. Do NOT split the ground plane into separate analog and digital regions (the old split-ground method is now recognized as counterproductive for most designs). Why? At RF frequencies: the return current for each signal naturally follows the path of minimum impedance, which is directly under the signal trace on the solid ground plane. The RF return current stays under the RF traces. The digital return current stays under the digital traces. They do NOT mix on a solid ground plane (they remain naturally separated). A split forces the return current to detour around the split, creating a large radiating loop and potential inter-circuit coupling (the exact problem the split was intended to prevent). (2) IC ground connections: for mixed-signal ICs (ADCs, DACs, transceivers) with separate AGND and DGND pins: connect BOTH AGND and DGND pins to the same solid ground plane directly under the IC. The IC manufacturer has designed the internal die layout to handle the analog-digital separation. The external ground must be low-impedance (solid plane) so the return currents flow freely through the IC without creating noise voltages. (3) Power supply separation: while the ground is unified, the power supplies SHOULD be separated. Use separate LDOs for the RF, analog, and digital power rails. The separate regulators prevent noise from the digital supply from coupling through the shared supply impedance to the RF and analog circuits. Each regulator output feeds its local circuits through a ferrite bead or inductor (providing additional high-frequency filtering).

Category: EMI, EMC, and Shielding

Updated: April 2026

Product Tie-In: PCB Materials, Capacitors, Ferrites

Mixed-Signal Grounding

The grounding strategy debate (split vs unified) has been definitively settled by modern PCB EMC research: a unified ground plane is superior for virtually all mixed-signal designs.

Historical Context

(1) The split ground method originated in the 1970s-1980s when: PCBs had only 2 layers (no ground plane). Components were large (DIP packages, through-hole). Frequencies were low (< 10 MHz). Sensitive circuits were analog (operational amplifiers, precision ADCs). In this context: separating the analog and digital grounds prevented digital switching current from flowing under analog circuits. The single-point (star) connection between the grounds prevented ground loops. (2) Modern PCBs have: 4-12+ layers with dedicated ground planes. SMD components (small loop areas). Frequencies from DC to GHz. RF circuits that require controlled-impedance transmission lines. In this context: a solid ground plane provides a low-impedance return path at all frequencies. The return current confinement (skin effect + proximity effect) naturally separates the RF and digital return currents without physical splits. (3) Component manufacturer guidance: all major mixed-signal IC manufacturers (Analog Devices, Texas Instruments, Linear Technology, Maxim, Infineon) recommend a unified ground plane in their application notes. The Analog Devices application note AN-202 and the TI application note SLYT499 are classic references that explain why split grounds are harmful for modern mixed-signal designs.

Return Current Path Analysis

(1) The return current for a high-speed digital signal (100 MHz clock) on Layer 1: flows on the Layer 2 ground plane directly under the trace. The current distribution is Gaussian, with 90% of the current within ±3H of the trace centerline (H = dielectric thickness). For H = 4 mil (0.1 mm): 90% of the return current is within ±0.3 mm of the trace. This means: a digital clock trace and an RF signal trace separated by 2 mm on the same layer have essentially non-overlapping return currents. They do not interfere through the ground plane. (2) If the ground plane is split between these two traces: the clock return current must detour around the split. The detour creates a loop that: radiates electromagnetic energy (the loop area is much larger than the trace-to-ground loop), picks up interference from other sources (the large loop couples to external fields), and crosses into the RF region (the detour path may run under RF components). The split ground creates the exact coupling it was intended to prevent.

Decoupling and Local Ground Return

(1) Decoupling capacitors provide a local ground return for the switching current of digital ICs. Place a 100 nF cap at each VCC pin, connecting VCC to GND with the shortest possible trace and via. The capacitor provides the charge for the switching transient locally, so the high-frequency current loop is: VCC pin → IC → GND pin → cap → VCC pin (loop area < 1 mm²). Without the decoupling cap: the current must flow from the power supply (far away) through the power plane, creating a large loop with significant radiation. (2) RF bypass capacitors: similar concept for RF circuits. Place 100 pF + 10 nF in parallel at each RF IC power pin. The 100 pF cap has lower impedance at GHz frequencies (higher SRF than the 10 nF). The combination provides low impedance from MHz to GHz. (3) Ground vias: every decoupling capacitor ground pad should connect to the ground plane through a direct via (not shared with signal vias). Use multiple vias for high-current or high-frequency decoupling (the via inductance limits the capacitor effectiveness at GHz frequencies).

Grounding Design Rules

Unified ground: Z_ground ≪ Z_signal at all f
Return current: 90% within ±3H of trace
Decoupling: 100nF @MHz, 100pF @GHz
Split ground penalty: 20-40 dB more coupling
Power separation: separate LDOs + ferrite beads

Common Questions

Frequently Asked Questions

My ADC datasheet says to use separate AGND and DGND. Does this mean split the ground?

No. The separate AGND and DGND pins are for internal die bonding purposes and to help with PCB component placement, NOT for split ground planes. Connect both AGND and DGND to the same solid ground plane. The IC is designed so that the analog return current flows through the AGND pins and the digital return current flows through the DGND pins. On the external ground plane: these currents naturally separate (the analog return stays near the analog pins, the digital return stays near the digital pins). If you split the ground and connect AGND to one region and DGND to another: the return current inside the IC must cross from one ground to the other, creating noise coupling within the IC. This degrades the ADC performance (higher noise, lower ENOB, more spurs).

When might I actually want a split ground?

The only scenario where a split ground may be beneficial: a PCB with a very high-power transmitter (> 10 W) and a very sensitive receiver (< -100 dBm) on the same board. The TX output current (amps) flows through the shared ground plane, creating voltage drops that couple into the receiver. In this case: separate ground regions connected at a single star point may reduce the coupling. But: all signal traces between the regions must cross through the star point. No traces may cross the split gap. This is complex to design and should only be attempted if the unified ground approach has been proven insufficient through measurement. For ALL other cases (99%+ of mixed-signal designs): use a unified ground.

Does the ground plane need to extend beyond the board edge?

The ground plane should extend to the board edge (no copper pullback required on ground layers for most fabricators). The ground plane at the board edge provides: a ground return path for edge-routed traces, a ground connection for perimeter-mounted connectors, and a ground for the shield can perimeter vias. Some fabricators require a small copper pullback from the board edge (0.2-0.5 mm) to prevent copper burrs during routing. This pullback is acceptable and does not significantly affect the ground plane performance. For critical EMI performance: extend the ground plane to the edge and specify the minimum pullback allowed by the fabricator.

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