EMI, EMC, and Shielding PCB EMC Design Informational

What is the role of decoupling capacitors in reducing EMI from power supply noise at RF frequencies?

Q: How many decoupling capacitors do I need per IC?

Rules of thumb: (1) For each power pin on the IC: at least one 100 nF capacitor. If the IC has 4 VCC pins: use 4 × 100 nF, one at each pin. (2) For the entire IC: add at least one bulk capacitor (10-47 uF) within 10 mm. (3) For high-speed digital ICs (FPGA, processor): add 1-3 additional high-frequency caps (1-10 nF, 100 pF) per power pin, placed as close as possible. (4) For RF ICs: follow the manufacturer evaluation board layout exactly. The decoupling scheme on the eval board has been optimized for that specific IC. Deviating from it risks performance degradation. (5) Total count: a high-speed FPGA with 50 power pins may have 100+ decoupling capacitors. An RF transceiver IC typically has 20-40 decoupling caps specified in the datasheet.

Q: Does the via from the capacitor to the ground plane matter?

Critically. The via adds inductance: approximately 0.5-1.0 nH per millimeter of via length. For a 1 mm via (typical 4-layer PCB): L_via ≈ 0.7 nH. At 1 GHz: Z_via = 2×pi×1e9 × 0.7e-9 = 4.4 ohms. This 4.4 ohms is in series with the capacitor, negating much of the decoupling benefit at 1 GHz. To minimize via inductance: use the shortest possible via (thin PCB or via-in-pad reduces the length). Use multiple vias per cap (two vias in parallel = half the inductance). Use the widest via drill possible (wider via = lower inductance). Some advanced designs use via-in-pad technology: the via is directly under the pad (zero trace length between cap and via), minimizing the total loop inductance to < 0.3 nH.

Q: What about decoupling above 5 GHz?

Above 5 GHz: discrete capacitors become less effective (even 01005 packages have SRF below 5-10 GHz). Decoupling above 5 GHz is provided by: (1) Power/ground plane capacitance: two planes separated by 2-4 mil dielectric create a distributed capacitor. C_plane = epsilon_0 × epsilon_r × Area / thickness. For a 50 × 50 mm area with 4 mil (0.1 mm) FR-4: C = 8.85e-12 × 4.2 × 0.0025 / 0.0001 = 930 pF distributed across the board. This provides smooth, resonance-free decoupling from 500 MHz to 10+ GHz. (2) Embedded capacitance materials: special thin laminates (Faradflex, 3M C-Ply) with high-Dk dielectric and 10 GHz). The PCB decoupling supplements the on-die decoupling at lower frequencies.

Decoupling capacitors provide a low-impedance path to ground for high-frequency noise on power supply lines, preventing the noise from reaching RF circuits and radiating as EMI. Operation: when an IC switches (digital transition, PA current pulse), it draws a transient current from the power supply. Without decoupling: the transient current flows through the entire power plane (large loop area = radiation), creating voltage noise on the supply that affects all ICs on the same rail. With decoupling: the local capacitor provides the instantaneous current (small loop area = minimal radiation), and the power supply replenishes the capacitor charge on a slower time scale. Key principles for RF frequencies: (1) Capacitor selection: the capacitor must present low impedance at the noise frequency. Z_cap = 1/(2×pi×f×C) for f < SRF, and Z_cap increases above SRF (inductive). For effective decoupling at 1 GHz: Z < 1 ohm requires C > 160 pF with SRF > 1 GHz. Use a 100 pF C0G 0402 capacitor (SRF ≈ 4 GHz). For effective decoupling at 100 MHz: C > 1.6 nF with SRF > 100 MHz. Use a 1 nF C0G 0402 (SRF ≈ 1.5 GHz). (2) Placement: the capacitor must be within 2 mm of the IC power pin (at 1 GHz: a 10 mm trace is lambda/30 = significant inductance). Shorter is always better. The via from the cap ground pad to the ground plane should be as short and wide as possible (minimize via inductance). (3) Multi-value strategy: no single capacitor covers the full noise spectrum (DC to multi-GHz). Use multiple capacitors in parallel with staggered values: 10 uF (electrolytic/tantalum): decouples below 1 MHz. 100 nF (MLCC X7R or C0G): decouples 1-100 MHz. 10 nF (MLCC C0G): decouples 10-500 MHz. 100 pF (MLCC C0G): decouples 100 MHz - 5 GHz. Place the smallest capacitor (highest frequency) closest to the IC pin.

Category: EMI, EMC, and Shielding

Updated: April 2026

Product Tie-In: PCB Materials, Capacitors, Ferrites

Decoupling for RF EMI Control

Decoupling capacitor design is one of the most critical yet often underappreciated aspects of RF PCB design. Poor decoupling leads to power supply noise that degrades receiver sensitivity, increases transmitter spurious emissions, and causes radiated EMI failures.

Impedance Analysis

The target impedance of the power distribution network (PDN) at each frequency is: Z_target = V_ripple_max / I_transient. For a 3.3 V supply with 33 mV maximum ripple (1%) and 1 A transient current: Z_target = 33 mV / 1 A = 33 milliohms. The PDN (power plane + decoupling capacitors) must present an impedance below Z_target at all frequencies from DC to the maximum clock frequency (and harmonics). At low frequencies (DC - 1 kHz): the voltage regulator provides low impedance. At medium frequencies (1 kHz - 10 MHz): bulk capacitors (10-100 uF) provide low impedance. At high frequencies (10 MHz - 1 GHz): MLCC decoupling caps (100 pF - 100 nF) provide low impedance. Above 1 GHz: the power plane capacitance (two planes separated by thin dielectric) provides distributed decoupling. For RF circuits: the VCO, PLL, and LNA are most sensitive to power supply noise. The noise on the supply modulates the VCO frequency (creating phase noise), modulates the LNA gain (creating AM noise), and can couple into the signal path directly.

Anti-Resonance Problem

When two capacitors of different values are placed in parallel: they create an anti-resonance at a frequency between their individual SRFs. At the anti-resonance: the impedance can be much higher than either capacitor alone (the inductive region of the large cap resonates with the capacitive region of the small cap). The anti-resonance impedance: Z_anti = Z_large × Q_eff, where Q_eff depends on the ESR of both capacitors. For low-ESR (C0G) capacitors: Q can be 50-100, creating anti-resonance impedance spikes of 10-100 ohms. This is WORSE than having no decoupling at that specific frequency. Mitigation: (1) Use capacitors with moderate ESR (X7R, or C0G with an added series resistor) to dampen the resonance. (2) Use a larger number of capacitor values to fill the anti-resonance gaps (e.g., 10 uF, 1 uF, 100 nF, 10 nF, 1 nF, 100 pF: six values create smoother impedance). (3) Use embedded capacitance (thin dielectric between power and ground planes): the distributed capacitance provides smooth, resonance-free decoupling above 500 MHz.

RF-Specific Decoupling

(1) VCO supply: the VCO supply must be extremely clean (< 10 uVrms noise in the VCO bandwidth). Use a dedicated linear regulator (LDO) for the VCO. Add multiple decoupling stages: at the regulator output: 10 uF + 100 nF. Between the regulator and the VCO: ferrite bead + 100 nF + 10 pF (creates a filtered section). At the VCO pin: 100 pF (closest to the pin). The ferrite bead provides lossy attenuation at RF frequencies (preventing RF from coupling back to the regulator and other circuits). (2) PA supply: the PA draws large current pulses (especially for modulated signals). The decoupling must supply the peak current without excessive voltage droop. For a 5G NR PA with 6 dB PAPR and 5 W average: peak current = 5 A (at 3.3 V supply). The decoupling cap must supply 5 A for the peak duration (< 1 us for a single OFDM symbol). Required capacitance: C > I × t / V_droop = 5 × 1e-6 / 0.033 = 150 uF. Use multiple 22-47 uF capacitors near the PA. (3) LNA supply: moderate decoupling (100 nF + 10 nF + 100 pF). The LNA draws only 10-50 mA, so the current transients are small. The concern is noise coupling from other circuits through the shared power plane. Use a ferrite bead to isolate the LNA supply from the main power bus.

Decoupling Design Equations

Z_cap = 1/(2πfC) for f < SRF
Z_target = V_ripple/I_transient
SRF = 1/(2π√(LC_ESL))
Placement: < 2 mm from IC pin
Multi-value: largest farther, smallest closest

Common Questions

Frequently Asked Questions

How many decoupling capacitors do I need per IC?

Rules of thumb: (1) For each power pin on the IC: at least one 100 nF capacitor. If the IC has 4 VCC pins: use 4 × 100 nF, one at each pin. (2) For the entire IC: add at least one bulk capacitor (10-47 uF) within 10 mm. (3) For high-speed digital ICs (FPGA, processor): add 1-3 additional high-frequency caps (1-10 nF, 100 pF) per power pin, placed as close as possible. (4) For RF ICs: follow the manufacturer evaluation board layout exactly. The decoupling scheme on the eval board has been optimized for that specific IC. Deviating from it risks performance degradation. (5) Total count: a high-speed FPGA with 50 power pins may have 100+ decoupling capacitors. An RF transceiver IC typically has 20-40 decoupling caps specified in the datasheet.

Does the via from the capacitor to the ground plane matter?

Critically. The via adds inductance: approximately 0.5-1.0 nH per millimeter of via length. For a 1 mm via (typical 4-layer PCB): L_via ≈ 0.7 nH. At 1 GHz: Z_via = 2×pi×1e9 × 0.7e-9 = 4.4 ohms. This 4.4 ohms is in series with the capacitor, negating much of the decoupling benefit at 1 GHz. To minimize via inductance: use the shortest possible via (thin PCB or via-in-pad reduces the length). Use multiple vias per cap (two vias in parallel = half the inductance). Use the widest via drill possible (wider via = lower inductance). Some advanced designs use via-in-pad technology: the via is directly under the pad (zero trace length between cap and via), minimizing the total loop inductance to < 0.3 nH.

What about decoupling above 5 GHz?

Above 5 GHz: discrete capacitors become less effective (even 01005 packages have SRF below 5-10 GHz). Decoupling above 5 GHz is provided by: (1) Power/ground plane capacitance: two planes separated by 2-4 mil dielectric create a distributed capacitor. C_plane = epsilon_0 × epsilon_r × Area / thickness. For a 50 × 50 mm area with 4 mil (0.1 mm) FR-4: C = 8.85e-12 × 4.2 × 0.0025 / 0.0001 = 930 pF distributed across the board. This provides smooth, resonance-free decoupling from 500 MHz to 10+ GHz. (2) Embedded capacitance materials: special thin laminates (Faradflex, 3M C-Ply) with high-Dk dielectric and < 1 mil thickness. Capacitance density: 1-5 nF/cm². Provides effective decoupling to 20+ GHz. (3) On-die decoupling: the IC itself has on-die capacitors (metal-oxide-metal or MOS capacitors) that provide the highest-frequency decoupling (> 10 GHz). The PCB decoupling supplements the on-die decoupling at lower frequencies.

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