How do I design a PCB layout to minimize electromagnetic interference between RF and digital sections?

Mixed-Signal PCB Layout

The PCB layout is the single most important factor in EMC performance for mixed-signal designs. A poorly laid-out board cannot be fixed with shielding or filtering after fabrication.

Component Placement Rules

(1) Place the crystal oscillator and clock generator IC as close to the MCU/FPGA clock input as possible. This minimizes the trace length carrying the extremely high-harmonic-content clock signal (a 100 MHz clock has significant energy at 300 MHz, 500 MHz, 1 GHz, and beyond). A long clock trace is a radiating antenna. (2) Place the VCO as far as possible from the digital section. The VCO is extremely sensitive to noise (1 mV of supply noise or substrate coupling can cause unacceptable phase noise). (3) Place the LNA input as far as possible from any power supply (especially switching DC-DC converters). The switching supply generates harmonic spurs that can couple into the LNA and degrade the receiver sensitivity. (4) Place the PA as close as possible to the antenna connector/feed. Long traces between the PA and antenna waste power (loss) and can radiate. (5) Place bypass/decoupling capacitors as close as possible to each IC power pin. The capacitor provides a local charge reservoir, reducing the current loop area for transient switching current.

Grounding and Power Distribution

(1) Unified ground: use a single, solid ground plane. Do NOT split the ground between analog, digital, and RF. The return current for each signal naturally flows under the signal trace on a solid ground plane (at RF frequencies). A split forces detours that increase coupling. (2) Power plane partitioning: while the ground is unified, the power distribution can be partitioned: separate power planes (or poured copper regions) for the RF supply, digital supply, and analog supply. Each power region is fed by its own voltage regulator (LDO for RF and analog, switching regulator acceptable for digital). This prevents high-frequency noise from the digital supply from reaching the RF circuits through shared supply impedance. (3) Star power routing: each voltage regulator connects to its load through a dedicated trace or plane region. The current paths do not overlap. This prevents the digital switching current (hundreds of mA at MHz rates) from flowing through the same trace as the RF supply current (tens of mA, must be ultra-clean).

Critical Signal Routing

(1) RF signal traces: route on microstrip (Layer 1) or stripline (inner layers). Maintain controlled impedance (50 ohms ±10%). Use ground plane return directly below the trace (Layer 2 ground). No vias, bends, or stubs in the signal path unless necessary (each discontinuity creates reflections and radiation). (2) High-speed digital traces: route on a layer with a ground plane directly adjacent. Use differential pairs for high-speed data (USB, PCIe, LVDS). Keep the differential pair spacing tight (minimize common-mode noise generation). (3) Separation between RF and digital: at minimum: 3H separation (H = dielectric height to the ground plane) for traces on the same layer. Better: route on different layers with a ground plane between them (> 40 dB isolation). Best: route on different layers with TWO ground planes between them (stripline isolation, > 60 dB). (4) Avoid parallel routing: if RF and digital traces must be near each other: cross at 90° (perpendicular crossing minimizes coupling to approximately one trace width of coupled length, vs full parallel coupling). Never route RF and digital traces in parallel on adjacent layers.

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