What is the effect of via stitching on the shielding effectiveness of a ground plane on a PCB?
Via Stitching for Ground Plane SE
Via stitching is one of the most important and often underutilized techniques for controlling EMI in multilayer PCBs. It is particularly critical for RF PCBs operating above 1 GHz.
Parallel-Plate Mode Suppression
Without stitching vias: the ground planes form a parallel-plate transmission line (PPL). The PPL supports TEM-mode propagation at all frequencies (no cutoff). A noise source (DC-DC converter, digital clock) at one location generates a wave that propagates across the entire ground plane system, reaching all circuits on the board. The PPL impedance is low (< 1 ohm) at most frequencies but has resonant peaks where the impedance can reach 10-100 ohms. At these resonant peaks: the power supply decoupling is ineffective, and significant noise appears on the supply rail. With stitching vias: the vias partition the PPL into a grid of small "cells." Each cell acts as a cavity with a cutoff frequency determined by the cell dimensions. Below the cutoff: no energy propagation between cells. The effective isolation between two cells separated by a via fence: SI = 20 × log10(sin(theta_space)) + loss terms, where theta_space = pi × d_via / lambda. For d_via = 2 mm at 5 GHz (lambda = 30 mm in free space, about 15 mm in FR-4): theta_space = pi × 2/15 = 0.42 radians. SI ≈ 20 × log10(0.42) = -7.5 dB. Not great isolation. For 20+ dB isolation: d_via must be < lambda/10 = 1.5 mm at 5 GHz.
Design Guidelines
(1) Via spacing: the universal rule is d_via < lambda/20 at the maximum operating frequency. This provides > 25 dB of isolation between ground plane regions. At 2.4 GHz (Wi-Fi, BLE): lambda_eff ≈ 60 mm on FR-4. d_via < 3 mm. At 5.8 GHz (Wi-Fi 6E): lambda_eff ≈ 25 mm. d_via < 1.25 mm. At 28 GHz (5G mmWave): lambda_eff ≈ 5 mm. d_via < 0.25 mm. At mmWave: the via spacing becomes extremely tight and may require HDI (high-density interconnect) PCB technology with microvias (0.1 mm drill, 0.2 mm pitch). (2) Via pattern: regular grid: easiest to implement. Provides uniform suppression across the board. Staggered grid (offset rows): slightly better suppression per unit area (the effective cell size is smaller). Perimeter fence: a dense row of vias around the board edge, around RF sections, and around shield can footprints. The fence prevents edge coupling between the top and bottom of the board. (3) Floor planning: place stitching vias in areas without signal traces on the internal layers. If a signal trace must cross the via grid: route the trace between vias (the vias create keep-out zones for routing). For dense boards: use buried or blind vias that do not occupy routing space on all layers.
Measurement and Verification
To verify that the via stitching is effective: (1) Measure the power plane impedance (Z_pp) with a VNA: connect a VNA probe to the power plane at two points (one near the noise source, one near the sensitive circuit). Measure S21 (the transfer impedance). Without stitching: S21 will show resonant peaks where the impedance is high (noise coupling is strong). With stitching: the resonant peaks shift to higher frequencies and are damped. S21 should be < -40 dB at all frequencies within the operating range. (2) Time-domain measurement: inject a pulse (from a clock generator) at one point on the power plane. Measure the transient voltage at another point using a high-speed oscilloscope probe. Without stitching: the transient propagates with standing waves. With stitching: the transient is attenuated and does not propagate beyond the local cell.
f_cutoff ≈ c/(2·d_via·√ε_r)
λ_eff = λ₀/√ε_r
Isolation ≈ 20log₁₀(sin(πd/λ_eff))
Resonance: f_mn = c/(2√ε_r)·√((m/a)²+(n/b)²)
Frequently Asked Questions
How many stitching vias do I need?
The total number depends on the board area and the required via spacing: for a 100 × 80 mm board with 2 mm via spacing: grid density = (100/2+1) × (80/2+1) = 51 × 41 = 2091 vias. This sounds like a lot, but ground vias are simple (no-connect, no routing) and cost nothing extra in standard PCB fabrication (the drill file is slightly larger). For a 50 × 50 mm module at 28 GHz with 0.5 mm spacing: 101 × 101 = 10,201 vias. This requires HDI technology. In practice: not every grid position needs a via. Place vias in available space (between signal traces, in unused routing areas). A 50-70% fill of the ideal grid still provides significant improvement over no stitching.
Do stitching vias affect signal routing?
Yes. Each stitching via occupies routing space on every layer it passes through. For a through-hole via (0.3 mm drill, 0.6 mm pad, 0.2 mm clearance): the keep-out zone is approximately 1.0 mm diameter. With 2 mm spacing: approximately 25% of each layer routing area is consumed by via keep-outs. This can be a problem for dense boards. Mitigation: use blind/buried vias for stitching (they only occupy space on the layers they connect, freeing routing on other layers). Use microvias (0.1 mm drill, 0.25 mm pad): smaller keep-out. Some designers use a "field of vias" approach: flood the empty routing areas with stitching vias after signal routing is complete. This maximizes the stitching density without affecting signal routing.
Is via stitching the same as via fencing?
No, they are different (but complementary): via stitching: ground vias distributed across the entire board area in a grid pattern. Purpose: suppress parallel-plate mode propagation and cavity resonances across the ground plane system. It is an area fill of vias. Via fencing: a perimeter row of closely-spaced ground vias around a specific region (around a shield can footprint, around a sensitive component, or around the board edge). Purpose: create a "wall" that prevents electromagnetic energy from entering or leaving the fenced region. It is a linear barrier of vias. Both are needed: the fence isolates the region, and the stitching suppresses modes within the region. A shield can with a via fence perimeter but no internal stitching: the cavity inside the shield can resonante, potentially making coupling worse at the resonant frequency.