What is the difference between an integer-N and a fractional-N frequency synthesizer?
Synthesizer Architecture Comparison
The integer-N PLL has a fundamental limitation: the comparison frequency determines both the frequency resolution and the maximum loop bandwidth. For 1 kHz frequency steps at a 2 GHz output: N = 2,000,000. The noise multiplication is 20·log10(2,000,000) = 126 dB, making the in-band noise very poor. The loop bandwidth cannot exceed about 100 Hz (fcomp/10), which severely limits the ability to suppress the VCO's close-in phase noise.
The fractional-N PLL breaks this constraint by using a much higher comparison frequency (typically 10-100 MHz) with a fractional division ratio. A 2 GHz output with 1 kHz resolution can use fcomp = 100 MHz with N = 20.00001. The noise multiplication is only 20·log10(20) = 26 dB, a 100 dB improvement. The loop bandwidth can be 100 kHz or wider, effectively suppressing the VCO's close-in noise.
The challenge with fractional-N is quantization noise from the divider modulation. The instantaneous division ratio switches between integers (e.g., 20 and 21), and this switching creates spurious phase noise. Delta-sigma modulation shapes the quantization noise to higher frequences where the loop filter attenuates it, but residual spurs and shaped noise remain. Higher-order delta-sigma modulators (3rd, 4th order) provide better noise shaping at the cost of wider noise energy distribution.
Frequently Asked Questions
When should I use integer-N?
When the required frequency step is large enough to allow a high comparison frequency. For example: 1 MHz steps at 1-2 GHz (N = 1000-2000). Also for ultra-low-spur applications where the quantization noise of fractional-N is unacceptable (radio astronomy, precision test equipment).
What are fractional spurs?
Fractional spurs are discrete spectral lines that appear near the carrier due to periodic patterns in the divider modulation. They are worst at fractions with small denominators (N+1/4, N+1/3) and minimum at large denominators. Modern PLL chips include spur-reduction techniques (random dithering, spur-avoidance algorithms) that reduce fractional spurs to -60 to -80 dBc.
What about direct digital synthesis (DDS)?
DDS generates frequencies by directly computing waveform samples from a digital accumulator and converting them to analog with a DAC. DDS provides very fine frequency resolution (micro-Hertz) with fast switching (nanoseconds). However, DDS is limited in output frequency by the DAC speed (typically below 1-3 GHz directly) and has higher spurious content than PLL-based synthesizers.