How does the reference oscillator quality affect the phase noise of a PLL synthesizer?
Reference Noise Impact
The PLL transfers the reference oscillator's phase noise to the output signal, multiplied by the division ratio. This noise multiplication is the fundamental limitation of the PLL architecture: higher output frequencies require larger N, which degrades the in-band phase noise. This is why high-frequency PLLs with small frequency steps (requiring large N) have poor close-in phase noise.
| Parameter | Passive Diode | Active FET | Subharmonic |
|---|---|---|---|
| Conversion Loss/Gain | 5-9 dB loss | 0-10 dB gain | 8-12 dB loss |
| LO Drive Level | +7 to +17 dBm | -5 to +5 dBm | +5 to +13 dBm |
| IP3 (typical) | +15 to +30 dBm | +5 to +20 dBm | +10 to +20 dBm |
| Noise Figure | 5-9 dB (= conv. loss) | 8-15 dB | 9-14 dB |
| LO-RF Isolation | 25-45 dB | 15-35 dB | 20-40 dB |
Frequently Asked Questions
When do I need an OCXO?
When the in-band phase noise specification cannot be met with a TCXO after N multiplication. For radar LOs requiring -130 dBc/Hz at 10 kHz offset at 10 GHz (N=1000): reference noise must be < -130 - 60 = -190 dBc/Hz, which is beyond any crystal oscillator. In this case, low-N architectures (direct multiplication from a high-frequency OCXO) or DRO/sapphire oscillators are needed.
Does the PLL chip add noise?
Yes. The PLL chip's phase-frequency detector (PFD) and charge pump add their own noise floor, specified as the PLL's 'in-band noise floor' or 'normalized phase noise.' Modern PLL chips (ADF4351, LMX2594) achieve -220 to -230 dBc/Hz normalized noise floor. This noise is multiplied by N² and can dominate over the reference noise for large N values.
Can I use multiple references?
Yes. Some synthesizers use multiple reference oscillators or cross-reference between GPS-disciplined and free-running OCXOs to achieve both excellent short-term (phase noise) and long-term (frequency accuracy) performance.