What is a direct digital synthesizer and when would I use it instead of a PLL?
DDS Architecture
The DDS consists of a phase accumulator (digital counter), a phase-to-amplitude converter (sine lookup table or CORDIC algorithm), and a DAC. The phase accumulator increments by a frequency tuning word (FTW) each clock cycle: phase(n) = phase(n-1) + FTW. The output frequency is fout = FTW × fclk / 2^N, where N is the accumulator bit width (typically 32-48 bits). This provides frequency resolution of fclk/2^N (sub-micro-Hertz for 48-bit accumulators).
Phase noise of a DDS is determined by the clock source at close-in offsets and by the DAC quantization noise at far-out offsets. A DDS clocked by a low-noise crystal oscillator achieves excellent close-in phase noise but has a noise floor set by the DAC's signal-to-noise ratio. Modern 14-bit DACs achieve 70+ dB SNR, giving a noise floor of approximately -150 dBc/Hz at far offsets.
The primary DDS limitation is spurious signals caused by DAC quantization, phase truncation, and DAC nonlinearity. These spurs appear at frequencies related to the output frequency and the clock frequency, and they cannot be filtered because they fall close to the desired output. Careful frequency planning and dithering techniques reduce the worst-case spur level.
Frequently Asked Questions
Can I use a DDS to generate microwave frequencies?
Not directly for most DDS chips (output limited to 1-3 GHz). Use a DDS as a fine-tuning reference for a PLL (hybrid DDS-PLL architecture): the DDS provides fine frequency resolution and fast switching, while the PLL multiplies to the final microwave frequency with clean spectral output.
What about power consumption?
DDS power consumption is dominated by the DAC and clock distribution: typically 0.5-3W for GHz-class DDS chips. This is significantly more than a simple PLL (<100 mW) but acceptable for most applications. Lower-frequency DDS chips consume tens of milliwatts.
How fast can a DDS switch frequency?
A DDS switches frequency in one clock cycle (sub-nanosecond for GHz clocks). The practical switching speed is limited by the digital interface (SPI typically: 1-10 μs to load a new FTW). Parallel-load DDS chips achieve <100 ns switching. This is 100-1000× faster than PLL settling.