Semiconductor and Device Technology III-V Semiconductors Informational

What is the role of silicon CMOS in millimeter wave applications and when can it replace III-V technologies?

Silicon CMOS has emerged as a viable mmWave technology for certain applications, driven by transistor scaling (fT > 300 GHz for 28 nm CMOS, > 400 GHz for 14 nm FinFET) and the massive integration advantage: (1) CMOS strengths: integration: a single CMOS die can contain the PA, LNA, mixer, VCO, PLL, ADC, DAC, digital beamforming, and DSP. Billions of transistors on one chip. No other technology can match this level of integration. Cost at volume: CMOS is fabricated on 12-inch wafers in existing fabs. The per-die cost at high volume is 10-100× lower than III-V. This enables mmWave functionality in consumer devices (smartphones, laptops) at acceptable cost. Digital integration: the same die that performs RF functions also performs digital signal processing. This eliminates the RF-to-digital interface (saving power, area, and cost). (2) CMOS limitations: output power: CMOS transistors have low breakdown voltage (1.2-3.3 V for standard nodes). Maximum output power per transistor: -10 to +5 dBm. Power combining is needed for any meaningful PA output (combining 4-64 unit cells to achieve +10 to +20 dBm). The combining losses reduce efficiency. PAE: CMOS PAs have lower PAE than III-V (10-20% vs 25-40% for GaAs/GaN at 28 GHz). The low PAE increases power consumption and heat generation. Noise figure: CMOS LNAs have higher NF than III-V (3-5 dB vs 0.5-2 dB at 28 GHz for GaAs pHEMT). The higher NF reduces receiver sensitivity. Passive quality: CMOS back-end metal is thin and has high sheet resistance compared to III-V (thick Au metallization). This reduces the Q of on-chip inductors, transmission lines, and matching networks. Substrate loss: the Si substrate is conductive (even HR-Si has lower resistivity than III-V semi-insulating substrates). Substrate coupling degrades isolation and increases loss. (3) Where CMOS replaces III-V: consumer 5G mmWave: CMOS (and closely related SiGe BiCMOS) is used for the integrated beamforming RFIC in smartphones. The PA output per element is low (< +15 dBm), and the integration advantage outweighs the efficiency penalty. 60 GHz WiGig: CMOS transceivers for IEEE 802.11ad/ay. The entire transceiver (including phased array) is on a single CMOS die. Automotive 77 GHz radar: CMOS-based radar SoCs (including TI AWR1843 in SiGe BiCMOS and some future designs in CMOS) integrate the entire radar on a single chip. (4) Where III-V remains essential: high-power PAs (> 5 W): GaN. Ultra-low-noise LNAs (NF < 1 dB): GaAs pHEMT or InP HEMT. Frequencies above 100 GHz: InP HEMT/HBT. High linearity applications: GaAs HBT.
Category: Semiconductor and Device Technology
Updated: April 2026
Product Tie-In: Transistors, MMICs, Evaluation Boards

Si CMOS at mmWave

The CMOS revolution at mmWave is driven by economics: the superior performance of III-V is traded for the massively lower cost and higher integration of CMOS in high-volume applications.

ParameterOption AOption BOption C
PerformanceHighMediumLow
CostHighLowMedium
ComplexityHighLowMedium
BandwidthNarrowWideModerate
Typical UseLab/militaryConsumerIndustrial

Technical Considerations

(1) 65 nm bulk CMOS: fT ≈ 200 GHz. Suitable for 60 GHz (V-band) applications. The first generation of CMOS 60 GHz transceivers (2008-2012). Limited PA output and efficiency. (2) 28 nm bulk/SOI CMOS: fT ≈ 300 GHz, fmax ≈ 350 GHz. Suitable for 28-39 GHz 5G. Good balance of RF performance and digital density. Used in: Qualcomm 5G RFIC, some radar front-ends. (3) 16/14 nm FinFET: fT > 350 GHz, fmax > 400 GHz. Excellent mmWave performance. The FinFET structure provides higher current drive and better output resistance than planar MOSFET. But: lower breakdown voltage (< 1.2 V for standard VDD). Used in: advanced 5G baseband + RF integration. (4) 7 nm and below: fT > 400 GHz. Increasingly used for digital processing with some RF functionality. The extremely low VDD (0.7-0.9 V) limits the PA output power to niveles below a few dBm per transistor. For PA: thick-oxide (IO) transistors with higher VDD (1.8-3.3 V) are used, but these have lower fT. (5) SOI CMOS: silicon-on-insulator provides a buried oxide layer that isolates the transistor from the substrate. Advantages: reduced substrate coupling, higher Q passives, and better isolation. GlobalFoundries 22FDX and similar processes are popular for RF-SOI switches and LNAs.

Performance Analysis

SiGe BiCMOS combines SiGe HBT (for high-performance analog/RF) with CMOS (for digital) on the same die: SiGe HBT: fT = 300-500 GHz, fmax = 400-700 GHz. Much higher than CMOS at the same node. The HBT provides: higher breakdown voltage (1.8-3.3 V for the HBT vs 1.2 V for CMOS), lower 1/f noise (important for VCOs), and higher transconductance per unit current. SiGe BiCMOS is the dominant technology for current 5G mmWave beamforming ICs, automotive 77 GHz radar, and precision instrumentation. The cost: SiGe BiCMOS is 20-50% more expensive than pure CMOS (additional SiGe epitaxy and process steps). But: much cheaper than III-V (processed on 8-12 inch Si wafers). Companies: Infineon (77 GHz radar), NXP (radar, 5G), Analog Devices (beamforming), and Qualcomm (5G mmWave).

Design Guidelines

When evaluating the role of silicon cmos in millimeter wave applications and when can it replace iii-v technologies?, engineers must account for the specific requirements of their target application. The optimal choice depends on the frequency range, power level, environmental conditions, and cost constraints of the overall system design.

Implementation Notes

When evaluating the role of silicon cmos in millimeter wave applications and when can it replace iii-v technologies?, engineers must account for the specific requirements of their target application. The optimal choice depends on the frequency range, power level, environmental conditions, and cost constraints of the overall system design.

  • Performance verification: confirm specifications against the application requirements before finalizing the design
  • Environmental factors: temperature range, humidity, and vibration affect long-term reliability and parameter drift
  • Cost vs. performance: evaluate whether the application demands premium components or standard commercial grades
  • Interface compatibility: verify impedance, connector type, and mechanical form factor match the system architecture

Practical Applications

When evaluating the role of silicon cmos in millimeter wave applications and when can it replace iii-v technologies?, engineers must account for the specific requirements of their target application. The optimal choice depends on the frequency range, power level, environmental conditions, and cost constraints of the overall system design.

Common Questions

Frequently Asked Questions

Will CMOS completely replace III-V?

No. CMOS will dominate in high-volume, cost-sensitive applications where integration is paramount: consumer 5G, automotive radar, and Wi-Fi. III-V will remain essential for: high-power applications (> 5 W): GaN is the only technology with adequate power density. CMOS cannot efficiently generate > 1 W per die at mmWave. Ultra-low noise: GaAs and InP will maintain their NF advantage (fundamental material properties, not a scaling issue). Frequencies above 200 GHz: InP is the only technology with useful gain. Military and space: where absolute performance matters more than cost. The future is heterogeneous integration (chiplet approach): CMOS for digital and beamforming control, SiGe for the transceiver, and GaN/GaAs for the PA and LNA. These die are co-packaged in an advanced SiP (system-in-package).

How does CMOS PA efficiency compare to GaAs?

At 28 GHz: CMOS PA (28 nm): PAE = 10-18% at P_sat. SiGe PA: PAE = 15-25% at P_sat. GaAs HBT PA: PAE = 25-35% at P_sat. GaN HEMT PA: PAE = 25-40% at P_sat. The gap: CMOS PAE is approximately half that of GaAs/GaN. For a 5G UE with 4 PA elements at +12 dBm each: CMOS PA total DC power: 4 × 16mW / 0.15 = 427 mW. GaAs PA total DC power: 4 × 16mW / 0.30 = 213 mW. The CMOS PA uses 2× more DC power for the same RF output. This means: shorter battery life, more heat, and potentially thermal throttling. The trade-off: CMOS saves $2-$5 per die (vs a separate GaAs PA die). The cost saving is worth it at volumes > 10 million units/year (the total cost saving >> the additional battery/thermal cost).

What about RF-SOI for mmWave?

RF-SOI (Radio Frequency Silicon-on-Insulator): a technology where MOSFET transistors are fabricated on a thin silicon layer above a buried oxide (BOX). Advantages for mmWave switches: the BOX isolates the transistor from the lossy Si substrate, enabling high-Q passives and excellent switch isolation, and low parasitic capacitance for fast switching. Performance: switch insertion loss < 1 dB at 28 GHz, isolation > 25 dB, and power handling > +30 dBm (using stacked-FET topology). RF-SOI is the dominant technology for mmWave switches and tunable components (tunable filters, antenna tuners). Limitations: the SOI transistor fT is typically lower than bulk CMOS at the same node (the thin body reduces the current drive). PA and LNA performance is inferior to SiGe and III-V. Best use: RF-SOI for switches + SiGe or III-V for PA/LNA = optimal system partitioning.

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