What is the role of silicon CMOS in millimeter wave applications and when can it replace III-V technologies?

Silicon CMOS has emerged as a viable mmWave technology for certain applications, driven by transistor scaling (fT > 300 GHz for 28 nm CMOS, > 400 GHz for 14 nm FinFET) and the massive integration advantage: (1) CMOS strengths: integration: a single CMOS die can contain the PA, LNA, mixer, VCO, PLL, ADC, DAC, digital beamforming, and DSP. Billions of transistors on one chip. No other technology can match this level of integration. Cost at volume: CMOS is fabricated on 12-inch wafers in existing fabs. The per-die cost at high volume is 10-100× lower than III-V. This enables mmWave functionality in consumer devices (smartphones, laptops) at acceptable cost. Digital integration: the same die that performs RF functions also performs digital signal processing. This eliminates the RF-to-digital interface (saving power, area, and cost). (2) CMOS limitations: output power: CMOS transistors have low breakdown voltage (1.2-3.3 V for standard nodes). Maximum output power per transistor: -10 to +5 dBm. Power combining is needed for any meaningful PA output (combining 4-64 unit cells to achieve +10 to +20 dBm). The combining losses reduce efficiency. PAE: CMOS PAs have lower PAE than III-V (10-20% vs 25-40% for GaAs/GaN at 28 GHz). The low PAE increases power consumption and heat generation. Noise figure: CMOS LNAs have higher NF than III-V (3-5 dB vs 0.5-2 dB at 28 GHz for GaAs pHEMT). The higher NF reduces receiver sensitivity. Passive quality: CMOS back-end metal is thin and has high sheet resistance compared to III-V (thick Au metallization). This reduces the Q of on-chip inductors, transmission lines, and matching networks. Substrate loss: the Si substrate is conductive (even HR-Si has lower resistivity than III-V semi-insulating substrates). Substrate coupling degrades isolation and increases loss. (3) Where CMOS replaces III-V: consumer 5G mmWave: CMOS (and closely related SiGe BiCMOS) is used for the integrated beamforming RFIC in smartphones. The PA output per element is low (< +15 dBm), and the integration advantage outweighs the efficiency penalty. 60 GHz WiGig: CMOS transceivers for IEEE 802.11ad/ay. The entire transceiver (including phased array) is on a single CMOS die. Automotive 77 GHz radar: CMOS-based radar SoCs (including TI AWR1843 in SiGe BiCMOS and some future designs in CMOS) integrate the entire radar on a single chip. (4) Where III-V remains essential: high-power PAs (> 5 W): GaN. Ultra-low-noise LNAs (NF < 1 dB): GaAs pHEMT or InP HEMT. Frequencies above 100 GHz: InP HEMT/HBT. High linearity applications: GaAs HBT.