Digital and Mixed Signal RF ADC and DAC for RF Informational

What is the interleaving technique for ADCs and how does it increase effective sampling rate?

Time-interleaved ADCs (TI-ADCs) use M parallel ADC channels, each sampling at f_s/M, with staggered sample timing to achieve an effective sampling rate of f_s. For example: four 1 GSPS ADCs interleaved to create a 4 GSPS system. The challenge: mismatches between the channels create spurs. Offset mismatch: creates a fixed DC offset spur. Gain mismatch: creates an image spur at f_s/2 - f_signal (for 2-way interleaving) or at f_s/M - f_signal (for M-way). Timing mismatch (skew): creates spurs whose amplitude increases with input frequency, limiting the effective bandwidth. Calibration: foreground calibration measures and corrects mismatches using known test signals. Background calibration continuously estimates and corrects mismatches during operation. Modern TI-ADC ICs include built-in background calibration achieving < -70 dBc interleaving spurs.
Category: Digital and Mixed Signal RF
Updated: April 2026
Product Tie-In: ADCs, DACs, Clock Sources

Interleaved ADCs

The timing mismatch spur amplitude is approximately: Spur_dBc ≈ 20·log10(π × f_in × Δt), where f_in is the input frequency and Δt is the timing mismatch. For 1 ps timing skew at 2 GHz input: spur level = 20·log10(π × 2×10⁹ × 1×10⁻¹²) = -50 dBc. This shows why timing calibration is critical at high input frequencies. Sub-100 fs calibration accuracy is needed for > 70 dBc spur suppression at multi-GHz input frequencies.

ParameterPipeline ADCSAR ADCSigma-Delta ADC
Sample Rate100 MS/s - 10 GS/s1-100 MS/s10 kS/s - 50 MS/s
Resolution8-14 bits10-20 bits16-24 bits
LatencySeveral clock cycles1 conversion cycleMany cycles (decimation)
PowerHighLow-moderateLow
Typical RF UseDirect sampling, DPDControl, monitoringAudio, baseband
  • Performance verification: confirm specifications against the application requirements before finalizing the design
  • Environmental factors: temperature range, humidity, and vibration affect long-term reliability and parameter drift
  • Cost vs. performance: evaluate whether the application demands premium components or standard commercial grades
  • Interface compatibility: verify impedance, connector type, and mechanical form factor match the system architecture
Common Questions

Frequently Asked Questions

How many channels can I interleave?

Practical TI-ADCs use 2 to 64 channels. Monolithic TI-ADCs (single chip): typically 2-4 channels. Board-level interleaving: up to 16-64 channels (used in oscilloscopes and wideband SIGINT receivers). More channels increase the calibration complexity and the number of interleaving spur frequencies.

Can I interleave ADCs from different manufacturers?

Technically possible but extremely difficult. The mismatches between different ADC types are large and temperature-dependent, requiring sophisticated calibration. In practice, TI-ADCs use identical ADC channels on the same die (monolithic interleaving) for best matching.

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