How does jitter on the ADC sampling clock affect the noise floor of a digital receiver?
ADC Clock Jitter Impact
Clock jitter is the single most critical performance parameter for the clock source in a high-frequency digital receiver. The clock quality directly determines the receiver dynamic range.
| Parameter | Pipeline ADC | SAR ADC | Sigma-Delta ADC |
|---|---|---|---|
| Sample Rate | 100 MS/s - 10 GS/s | 1-100 MS/s | 10 kS/s - 50 MS/s |
| Resolution | 8-14 bits | 10-20 bits | 16-24 bits |
| Latency | Several clock cycles | 1 conversion cycle | Many cycles (decimation) |
| Power | High | Low-moderate | Low |
| Typical RF Use | Direct sampling, DPD | Control, monitoring | Audio, baseband |
Frequently Asked Questions
How do I measure clock jitter?
Methods: (1) Phase noise analyzer: directly measures the phase noise spectrum L(f_offset) of the clock signal. Integrate the phase noise over the bandwidth to calculate RMS jitter. This is the most accurate method. Instruments: Rohde & Schwarz FSWP, Keysight E5052B. (2) High-speed oscilloscope: measure the clock waveform and compute the jitter histogram from the zero-crossing timing variations. The oscilloscope must have much lower jitter than the DUT (trigger jitter < 10 fs for measuring 50 fs clock jitter). Instruments: Keysight UXR, Tektronix DPO70000. (3) ADC-based measurement: sample the clock (or a known signal clocked by the clock) with a high-resolution ADC. Analyze the SNR of the sampled signal. The jitter-limited SNR reveals the effective jitter: t_j = 1/(2pi × f_in × 10^(SNR/20)). This measures the total jitter (clock + distribution + ADC aperture), which is the relevant parameter for the receiver design.
Can I filter clock jitter?
The PLL that generates the sampling clock acts as a jitter filter: (1) Inside the PLL loop bandwidth (f_offset < f_BW): the PLL cleans the input reference jitter (the VCO tracks the reference, filtering out its noise). High loop bandwidth: more jitter cleaning at low offsets, but the VCO noise at high offsets passes through. (2) Outside the PLL loop bandwidth (f_offset > f_BW): the output jitter is dominated by the VCO free-running noise. Low loop bandwidth: better VCO noise filtering, but the reference jitter at low offsets passes through. Optimal PLL bandwidth: set the loop bandwidth at the offset frequency where the reference noise and VCO noise are equal. This minimizes the total integrated phase noise. For a crystal reference with L = -155 dBc/Hz at 100 kHz and a VCO with L = -110 dBc/Hz at 100 kHz: the crossover is near 10-50 kHz. Set the PLL BW to approximately 20 kHz. After the PLL: add a clean-up PLL or a resonant SAW filter to further reduce jitter at specific offset frequencies.
What is phase noise vs jitter?
Phase noise and jitter describe the same phenomenon (clock timing uncertainty) in different domains: Phase noise L(f_offset) is the frequency-domain representation: the power spectral density of the phase fluctuations, measured in dBc/Hz at a specified offset frequency. Jitter t_j is the time-domain representation: the RMS variation in the timing of the clock edges. They are related by: t_j = (1/(2pi×f_clk)) × sqrt(2 × integral from f_low to f_high of 10^(L(f)/10) df). The integration bounds matter: f_low: typically 12 kHz (corresponding to the carrier bandwidth) or 100 Hz (for wideband jitter). f_high: f_clk/2 (Nyquist frequency). Different integration ranges give different jitter values. Always specify the integration range when quoting jitter numbers.