Digital and Mixed Signal RF ADC and DAC for RF Informational

How does jitter on the ADC sampling clock affect the noise floor of a digital receiver?

Q: How do I measure clock jitter?

Methods: (1) Phase noise analyzer: directly measures the phase noise spectrum L(f_offset) of the clock signal. Integrate the phase noise over the bandwidth to calculate RMS jitter. This is the most accurate method. Instruments: Rohde & Schwarz FSWP, Keysight E5052B. (2) High-speed oscilloscope: measure the clock waveform and compute the jitter histogram from the zero-crossing timing variations. The oscilloscope must have much lower jitter than the DUT (trigger jitter < 10 fs for measuring 50 fs clock jitter). Instruments: Keysight UXR, Tektronix DPO70000. (3) ADC-based measurement: sample the clock (or a known signal clocked by the clock) with a high-resolution ADC. Analyze the SNR of the sampled signal. The jitter-limited SNR reveals the effective jitter: t_j = 1/(2pi × f_in × 10^(SNR/20)). This measures the total jitter (clock + distribution + ADC aperture), which is the relevant parameter for the receiver design.

Q: Can I filter clock jitter?

The PLL that generates the sampling clock acts as a jitter filter: (1) Inside the PLL loop bandwidth (f_offset f_BW): the output jitter is dominated by the VCO free-running noise. Low loop bandwidth: better VCO noise filtering, but the reference jitter at low offsets passes through. Optimal PLL bandwidth: set the loop bandwidth at the offset frequency where the reference noise and VCO noise are equal. This minimizes the total integrated phase noise. For a crystal reference with L = -155 dBc/Hz at 100 kHz and a VCO with L = -110 dBc/Hz at 100 kHz: the crossover is near 10-50 kHz. Set the PLL BW to approximately 20 kHz. After the PLL: add a clean-up PLL or a resonant SAW filter to further reduce jitter at specific offset frequencies.

Jitter on the ADC sampling clock converts the phase noise of the clock into amplitude noise in the digitized signal, directly raising the noise floor of the digital receiver. The mechanism: (1) An ideal ADC samples the analog signal at perfectly uniform time intervals (T_s = 1/f_s). The digitized signal is an exact representation of the analog signal at each sampling instant. (2) A real ADC clock has jitter: the sampling instants are slightly early or late by a random amount (Δt). The jitter has an RMS value (t_j) and a spectral distribution (typically white noise from the clock oscillator, plus discrete spurs from the PLL). (3) When a signal at frequency f_in is sampled with clock jitter t_j: the sampled value deviates from the ideal by: Δv = dv/dt × Δt = 2×pi×f_in × A × cos(2×pi×f_in×t) × Δt. The error is proportional to the signal frequency (higher frequency signals are affected more because they change faster). (4) The SNR limitation from jitter: SNR_jitter = -20 × log10(2×pi×f_in×t_j_rms). For f_in = 1 GHz and t_j = 100 fs: SNR_jitter = -20×log10(2×pi×1e9×100e-15) = -20×log10(6.28e-4) = 64 dB. For f_in = 2 GHz and t_j = 100 fs: SNR_jitter = 58 dB. Each doubling of f_in reduces SNR by 6 dB. Each doubling of jitter reduces SNR by 6 dB. (5) Combined SNR: the total ADC SNR combines quantization noise, thermal noise, and jitter noise: 1/SNR_total² = 1/SNR_quantization² + 1/SNR_thermal² + 1/SNR_jitter². In a high-performance receiver: the jitter noise is often the dominant limitation (especially at high input frequencies). For a 14-bit ADC sampling a 1 GHz signal: quantization SNR ≈ 84 dB (ENOB ≈ 14). Thermal SNR ≈ 75 dB (from the ADC analog front end). Jitter SNR at 100 fs ≈ 64 dB. Total SNR ≈ 63 dB (dominated by jitter). The 14-bit ADC effectively becomes a 10-bit ADC (ENOB = (63-1.76)/6.02 = 10.2 bits) because of clock jitter.

Category: Digital and Mixed Signal RF

Updated: April 2026

Product Tie-In: ADCs, DACs, Clock Sources

ADC Clock Jitter Impact

Clock jitter is the single most critical performance parameter for the clock source in a high-frequency digital receiver. The clock quality directly determines the receiver dynamic range.

Jitter Sources

(1) Clock oscillator phase noise: the VCO or crystal oscillator that generates the sampling clock has phase noise. The integrated phase noise over the Nyquist bandwidth converts to RMS jitter: t_j = (1/(2×pi×f_clk)) × sqrt(2 × integral(L(f_offset) df)). Where L(f_offset) is the single-sideband phase noise (dBc/Hz) at offset frequency f_offset. For a low-noise clock: L(100kHz) = -155 dBc/Hz (crystal-based, very good). L(100kHz) = -130 dBc/Hz (PLL-based, moderate). Integrated jitter: crystal: 10-30 fs (excellent). PLL: 50-200 fs (acceptable for many applications). VCO without PLL: 200-1000 fs (poor for high-performance ADCs). (2) Clock distribution: the jitter added by the clock distribution network (buffers, fanout, PCB traces) can be significant. Each active buffer adds 10-50 fs of jitter. A long PCB trace picks up substrate noise coupling that adds jitter. Best practice: use a dedicated low-jitter clock buffer (SiGe or HCMOS), short trace from clock buffer to ADC clock input, and separate clock power supply (isolated from digital noise). (3) ADC internal jitter: the ADC itself adds jitter through its internal clock buffer and sampling switch. This is specified as "aperture jitter" on the ADC datasheet (typically 30-100 fs for high-performance ADCs). The total effective jitter: t_j_eff = sqrt(t_j_clock² + t_j_distribution² + t_j_aperture²).

Clock Requirements by Application

(1) Cellular base station (5G NR): input frequency: 0.5-4 GHz (direct sampling or IF sampling). Required SNR: > 65 dB (for 256-QAM EVM < -32 dB). Jitter requirement: for f_in = 2 GHz, SNR = 65 dB: t_j < 1/(2pi × 2e9 × 10^(65/20)) = 1/(2pi × 2e9 × 1778) = 44.8 fs. Use a crystal-based clock or a very low-noise PLL. (2) Radar ADC: input frequency: 1-77 GHz IF (beat frequency at baseband, typically 1-100 MHz). At f_beat = 50 MHz: t_j < 1/(2pi × 50e6 × 10^(70/20)) = 1 ps. Less demanding (because the IF frequency is low). Standard PLL clocks with < 500 fs jitter are adequate. (3) Software-defined radio (SDR): input frequency: 0.1-6 GHz (direct sampling). Required SNR: 70+ dB (for flexible wideband reception). Jitter: < 30 fs for direct sampling at 6 GHz. This is at the limit of current technology (only the best crystal oscillators achieve < 30 fs integrated jitter).

Jitter-SNR Equations

SNR_jitter = -20log₁₀(2πf_in·t_j)
f_in doubled → SNR drops 6 dB
t_j doubled → SNR drops 6 dB
ENOB_eff = (SNR_total - 1.76)/6.02
t_j_eff = √(t²_clk + t²_dist + t²_aperture)

Common Questions

Frequently Asked Questions

How do I measure clock jitter?

Methods: (1) Phase noise analyzer: directly measures the phase noise spectrum L(f_offset) of the clock signal. Integrate the phase noise over the bandwidth to calculate RMS jitter. This is the most accurate method. Instruments: Rohde & Schwarz FSWP, Keysight E5052B. (2) High-speed oscilloscope: measure the clock waveform and compute the jitter histogram from the zero-crossing timing variations. The oscilloscope must have much lower jitter than the DUT (trigger jitter < 10 fs for measuring 50 fs clock jitter). Instruments: Keysight UXR, Tektronix DPO70000. (3) ADC-based measurement: sample the clock (or a known signal clocked by the clock) with a high-resolution ADC. Analyze the SNR of the sampled signal. The jitter-limited SNR reveals the effective jitter: t_j = 1/(2pi × f_in × 10^(SNR/20)). This measures the total jitter (clock + distribution + ADC aperture), which is the relevant parameter for the receiver design.

Can I filter clock jitter?

The PLL that generates the sampling clock acts as a jitter filter: (1) Inside the PLL loop bandwidth (f_offset < f_BW): the PLL cleans the input reference jitter (the VCO tracks the reference, filtering out its noise). High loop bandwidth: more jitter cleaning at low offsets, but the VCO noise at high offsets passes through. (2) Outside the PLL loop bandwidth (f_offset > f_BW): the output jitter is dominated by the VCO free-running noise. Low loop bandwidth: better VCO noise filtering, but the reference jitter at low offsets passes through. Optimal PLL bandwidth: set the loop bandwidth at the offset frequency where the reference noise and VCO noise are equal. This minimizes the total integrated phase noise. For a crystal reference with L = -155 dBc/Hz at 100 kHz and a VCO with L = -110 dBc/Hz at 100 kHz: the crossover is near 10-50 kHz. Set the PLL BW to approximately 20 kHz. After the PLL: add a clean-up PLL or a resonant SAW filter to further reduce jitter at specific offset frequencies.

What is phase noise vs jitter?

Phase noise and jitter describe the same phenomenon (clock timing uncertainty) in different domains: Phase noise L(f_offset) is the frequency-domain representation: the power spectral density of the phase fluctuations, measured in dBc/Hz at a specified offset frequency. Jitter t_j is the time-domain representation: the RMS variation in the timing of the clock edges. They are related by: t_j = (1/(2pi×f_clk)) × sqrt(2 × integral from f_low to f_high of 10^(L(f)/10) df). The integration bounds matter: f_low: typically 12 kHz (corresponding to the carrier bandwidth) or 100 Hz (for wideband jitter). f_high: f_clk/2 (Nyquist frequency). Different integration ranges give different jitter values. Always specify the integration range when quoting jitter numbers.

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