Digital and Mixed Signal RF ADC and DAC for RF Informational

How do I select an ADC for a direct sampling RF receiver based on bandwidth and dynamic range?

A direct sampling (or direct conversion/direct digitization) RF receiver digitizes the RF signal directly at the antenna frequency without analog downconversion to an intermediate frequency. ADC selection requires balancing four key parameters: (1) Sampling rate: the ADC must sample at or above the Nyquist rate for the highest RF frequency of interest. For direct sampling at f_RF: f_sample >= 2 × f_RF. However: many direct sampling receivers use bandpass (undersampling) techniques where the ADC samples at a rate much lower than the RF frequency, using the aliasing phenomenon to fold the RF signal into the first Nyquist zone. Requirement: f_sample >= 2 × BW_signal (even if f_RF >> f_sample). The ADC analog input bandwidth must still support the RF frequency (the track-and-hold circuit must follow the full RF signal). Example: for a 2 GHz RF signal with 100 MHz bandwidth: direct sampling: f_sample > 4 Gsps (Nyquist for 2 GHz). Undersampling at 4th Nyquist zone: f_sample > 200 Msps (with analog bandwidth > 2 GHz). (2) SFDR (Spurious-Free Dynamic Range): the ratio between the desired signal and the largest spurious signal generated by the ADC. For a receiver that must detect weak signals in the presence of strong interference: SFDR > 80 dBc is typical for military/HF receivers. SFDR > 70 dBc for cellular base stations. SFDR limits the receiver instantaneous dynamic range (the ability to detect a weak signal when a strong interferer is present). (3) NSD (Noise Spectral Density): the ADC noise floor per Hz. NSD = -(SNR + 10×log10(f_sample/2)) dBm/Hz. For a 14-bit ADC at 250 Msps: SNR = 72 dB. NSD = -(72 + 10×log10(125e6)) = -(72 + 81) = -153 dBm/Hz. The receiver noise floor is the worse of the ADC NSD and the analog front-end noise floor (kTB + NF). (4) Analog input bandwidth: must exceed the highest RF frequency to be digitized. For HF receivers (0-30 MHz): > 30 MHz (any modern ADC). For VHF/UHF receivers (30-1000 MHz): > 1 GHz. For microwave direct sampling (1-3 GHz): > 3 GHz (requires specialized high-bandwidth ADCs).

Category: Digital and Mixed Signal RF

Updated: April 2026

Product Tie-In: ADCs, DACs, Clock Sources

ADC for Direct Sampling Receivers

Direct sampling receivers eliminate the analog mixer and local oscillator, replacing them with a high-performance ADC and digital signal processing. This simplifies the hardware and enables software-defined radio flexibility.

ADC Architectures for Direct Sampling

(1) Pipeline ADC: the traditional workhorse for high-speed, high-resolution ADCs. Resolution: 12-16 bits. Speed: 100 Msps - 5 Gsps. SFDR: 70-90 dBc (at lower input frequencies). Power: 0.5-3 W. Examples: Analog Devices AD9625 (12-bit, 2.6 Gsps, SFDR > 78 dBc), Texas Instruments ADC32RF45 (14-bit, 3 Gsps, SFDR > 75 dBc). Used for: direct sampling at VHF/UHF and L-band (up to 2 GHz). (2) SAR ADC: lower power than pipeline. Speed: up to 200 Msps (single core) or 1 Gsps (interleaved). Resolution: 12-18 bits. SFDR: 85-100+ dBc (exceptional SFDR at lower speeds). Power: 50-500 mW. Examples: Analog Devices LTC2387 (16-bit, 15 Msps, SFDR > 100 dBc). Used for: HF direct sampling (0-30 MHz) where maximum SFDR is critical. (3) Sigma-delta (bandpass): specialized for narrowband signals at specific frequencies. Very high resolution (16-24 bits) within a narrow bandwidth. Not suitable for wideband direct sampling. Used for: digital IF processing in some receiver architectures.

Undersampling (Bandpass Sampling)

(1) Concept: if the RF signal occupies a narrow bandwidth (BW) centered at a high carrier frequency (f_c), the ADC can sample at f_sample = 2 × BW (much less than 2 × f_c). The sampling process aliases the RF signal to a lower frequency in the first Nyquist zone: f_alias = f_c mod f_sample. The signal appears at f_alias with the same bandwidth and information content. (2) Requirements: the ADC analog bandwidth (not the sample rate) must support the input frequency. The ADC input has a track-and-hold circuit that tracks the RF signal. The aperture jitter must be very low: SNR_jitter = -20×log10(2×pi×f_c×sigma_j). For f_c = 2 GHz and SNR_jitter = 70 dB (adequate for 12-bit): sigma_j < 1/(2×pi×2e9 × 10^(70/20)) = 25 fs. This is extremely stringent. High-performance ADCs achieve 30-100 fs RMS jitter. (3) Anti-aliasing: a bandpass filter at the input is essential. The filter passes only the desired band and rejects all other signals and noise from aliasing into the same Nyquist zone. Without the filter: out-of-band noise and interferers fold on top of the desired signal, degrading the SNR. Filter requirements: steep skirts at the band edges (6th-8th order) and > 60 dB rejection outside the passband.

Direct Sampling Receiver Architecture

(1) Wideband direct sampling (0-3 GHz): antenna → LNA → anti-alias filter → ADC (3+ Gsps, 12-14 bits). Digital tuning (DDC in FPGA): select the desired channel by digital mixing and decimation filtering. This is a true software-defined radio (any signal within the 0-3 GHz range can be received by changing the digital tuner parameters). Used in: military wideband receivers, signals intelligence (SIGINT), and spectrum monitoring. (2) Narrowband direct sampling with undersampling: antenna → BPF (selects the RF band) → LNA → BPF (anti-alias) → ADC (200-500 Msps, 14-16 bits, analog BW > f_c). The ADC undersamples at a convenient rate, aliasing the RF to baseband. DDC in FPGA selects the specific channel. Used in: cellular base stations (some modern designs digitize at L-band after a single downconversion stage), and HF/VHF receivers. (3) Multi-band direct sampling: multiple parallel ADC channels, each covering a different frequency band. Digital beamforming and channelization in the FPGA. Used in: advanced AESA radar (each antenna element has its own ADC) and massive MIMO base stations.

Direct Sampling ADC Equations

f_sample ≥ 2×BW (Nyquist for BW)
NSD = -(SNR + 10log₁₀(f_s/2)) dBm/Hz
SNR_jitter = -20log₁₀(2πf_c·σ_j)
SFDR > 70-80 dBc for RF receivers
f_alias = f_c mod f_sample (bandpass)

Common Questions

Frequently Asked Questions

What ADCs are used for HF direct sampling receivers?

For HF (0-30 MHz): the gold standard is a high-SFDR, moderate-speed ADC: Analog Devices LTC2208 (16-bit, 130 Msps, SFDR > 100 dBc). AD9467 (16-bit, 250 Msps, SFDR > 90 dBc). Texas Instruments ADS5484 (16-bit, 170 Msps, SFDR > 92 dBc). These ADCs digitize the entire 0-65 MHz first Nyquist zone (at 130 Msps) or 0-125 MHz (at 250 Msps). All HF signals (AM, SSB, CW, digital modes) within the band are captured simultaneously. Digital channelization in an FPGA selects individual signals. This architecture is used in all modern HF receivers (tactical military radios, amateur radio SDR, and commercial HF monitoring).

Can I directly sample at microwave frequencies?

Increasingly, yes. Modern ADCs achieve > 10 Gsps with 8-12 bits: Analog Devices AD9213 (12-bit, 10.25 Gsps). TI ADC12DJ3200 (12-bit, 6.4 Gsps). These can directly sample signals up to 3-5 GHz (first/second Nyquist zone). The challenge is the SNR at high input frequencies: aperture jitter degrades the effective resolution. At 3 GHz input with 100 fs jitter: SNR_jitter = -20×log10(2×pi×3e9×100e-15) = 44 dB (approximately 7 ENOB). This limits the dynamic range compared to lower-frequency operation. For many applications (radar, EW): 7-8 ENOB at 3 GHz is adequate. For narrowband communications requiring high SFDR: undersampling or a single analog downconversion stage to a lower IF is still preferred.

How does the FPGA fit into a direct sampling receiver?

The FPGA performs the functions that were traditionally done by analog hardware: (1) Digital down-converter (DDC): a digital mixer + decimation filter that selects a specific channel from the wideband digitized spectrum. Multiple DDCs can run in parallel: one FPGA can tune to dozens of channels simultaneously. (2) Digital filtering: FIR/IIR filters with arbitrary frequency response (much sharper and more flexible than analog filters). (3) Channelization: polyphase filterbank or FFT-based channelizer that splits the wideband input into hundreds of narrowband channels simultaneously. (4) AGC: digital gain control with instant response (no settling time like analog AGC). (5) Demodulation: AM, FM, digital demodulation all in digital. The FPGA + ADC replace: multiple analog mixers, LOs, IF filters, and demodulators. The entire receiver is defined by the FPGA firmware (software-defined radio).

Keep Reading