Signal Integrity and High Speed Digital EMI from High Speed Digital Informational

What is the effect of simultaneous switching noise on the performance of an adjacent RF circuit?

What is the effect of simultaneous switching noise (SSN) on the performance of an adjacent RF circuit? SSN creates broadband voltage ripple on the power and ground planes that can couple into RF circuits, degrading receiver sensitivity, PA linearity, and LO phase noise: (1) SSN mechanism: when multiple digital outputs switch simultaneously, they draw large transient currents (ΔI). The voltage drop across the parasitic inductance of the PDN: ΔV = L_PDN × dI/dt. For 64 outputs switching 50 mA each with 100 ps rise time: dI/dt = 64 × 0.050 / 0.0001 = 32 kA/s. With L_PDN = 100 pH: ΔV = 100e-12 × 32e6 = 3.2 mV. With L_PDN = 1 nH (poor PDN): ΔV = 32 mV. This ΔV appears on the ground plane and propagates as a wave toward the RF circuits. (2) Impact on RF circuits: LO phase noise: the VCO supply or tuning voltage noise modulates the oscillator frequency. A 1 mV noise at 10 MHz offset on a 2.4 GHz VCO: can degrade phase noise by 5-10 dB. Receiver sensitivity: SSN on the LNA supply modulates the LNA gain, creating intermodulation products. SSN on the mixer supply creates spurious mixing products. PA linearity: SSN on the PA supply modulates the PA bias point, creating: AM/PM conversion (phase noise in the output spectrum), and spectral regrowth (increased ACLR). ADC performance: SSN on the ADC reference or supply degrades the ENOB (effective number of bits). 1 mV of SSN noise reduces a 12-bit ADC to approximately 11-bit performance. (3) Coupling paths: conducted (through PDN): the primary path for SSN to reach RF circuits. Mitigated by: ferrite bead isolation, separate LDOs, and extensive decoupling. Radiated (near-field coupling): SSN creates magnetic and electric near-field emissions from the digital IC and its traces. These fields couple to nearby RF traces and components. Mitigated by: physical separation, shielding, and ground stitching. Ground plane coupling: high-frequency SSN currents flow in the ground plane and can generate a ground voltage difference between the digital and RF sections. Mitigated by: low-impedance ground (thick copper, many vias), and avoiding ground plane slots.

Category: Signal Integrity and High Speed Digital

Updated: April 2026

Product Tie-In: PCB Materials, Shielding, Capacitors

SSN Impact on RF Circuits

SSN is the primary noise source from high-speed digital circuits and is responsible for the majority of digital-to-RF interference in mixed-signal designs.

Reducing SSN at the Source

(1) Reduce dI/dt: use slower edge rates (increase the output driver slew rate). Use output impedance matching (series resistors that limit the current transient). Stagger the switching timing (avoid all outputs switching on the same clock edge). (2) Reduce the number of simultaneously switching outputs: use registered outputs with slightly different clock delays. Use multi-phase clocking (different groups switch at different times). (3) Reduce L_PDN: use wide, short power traces (lower inductance). Place decoupling capacitors immediately adjacent to the IC power pins (reduces the loop inductance). Use power planes with many vias (reduces the plane inductance).

SSN Impact on RF

ΔV = L_PDN × dI/dt
64 pins × 50 mA, 100 ps → ΔV = 3.2 mV (100 pH)
1 nH PDN inductance: ΔV = 32 mV (critical)
1 mV on VCO: 5-10 dB phase noise degradation
Decoupling + ferrite: 30-50 dB SSN reduction

Common Questions

Frequently Asked Questions

How do I measure SSN on a PCB?

Use a near-field probe (magnetic loop probe, H-field probe) placed over the digital IC or the ground plane. The probe measures the time-varying magnetic field (proportional to the SSN current). Display on an oscilloscope (time domain) or spectrum analyzer (frequency domain). Compare the measured SSN spectrum to the RF receiver sensitivity requirements. If any SSN harmonic exceeds the receiver interference threshold: additional filtering or shielding is needed.

Is SSN worse in FPGAs or processors?

FPGAs (Xilinx, Intel): can have hundreds of simultaneously switching I/Os (especially in high-speed interfaces like DDR4/5 memory). SSN from an FPGA can be extremely severe. Processors (ARM, x86): have fewer external I/Os but higher clock frequencies and more internal switching. SSN on the processor PDN is high but primarily affects the processor itself (not adjacent RF, because processors are internally filtered). In mixed-signal designs: the FPGA DDR bus is typically the worst SSN source due to the large number of simultaneous edge transitions.

Can I use a power plane as a shield?

A solid power plane between a digital layer and an RF layer provides some shielding (similar to a ground plane). However: the power plane carries switching currents (SSN), which create their own magnetic fields. A power plane is a less effective shield than a ground plane. Preferred stackup: ground plane between every digital/RF signal layer pair. Avoid placing a signal layer between a power plane and a signal layer without a ground reference.

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