Signal Integrity and High Speed Digital EMI from High Speed Digital Informational

How do I design the power distribution network for a mixed signal PCB with both RF and high speed digital?

How do I design the power distribution network (PDN) for a mixed-signal PCB with both RF and high-speed digital? The PDN must provide clean, low-impedance power to both the RF and digital circuits while preventing noise coupling between them: (1) PDN requirements: RF circuits need: very low noise on the power supply (≤ 1-10 μV/√Hz at the frequency of interest). The power supply noise directly affects the LO phase noise, PA linearity, and receiver sensitivity. Digital circuits generate: high-current transients (simultaneous switching noise, SSN) that create voltage ripple on the PDN. These transients have spectral content from DC to the clock harmonics (> 10 GHz). The challenge: keeping the digital noise out of the RF supply while sharing the same PCB ground and power infrastructure. (2) PDN architecture: separate voltage regulators: use independent LDO (Low Drop-Out) regulators for RF supplies. LDOs provide 40-70 dB of supply noise rejection (PSRR) at frequencies below 1 MHz. Above 1 MHz: LDO PSRR degrades; rely on decoupling capacitors. Never power RF circuits from a switching regulator (buck/boost) output without additional filtering (switcher noise is 30-50 dB worse than LDO noise). Ferrite bead isolation: place a ferrite bead between the digital and RF power planes (or traces). The ferrite bead provides 10-30 dB of isolation at 100 MHz-1 GHz. Below the ferrite bead: use a bulk capacitor (10-100 μF) on the digital side, and decoupling caps (100 nF, 10 nF) on the RF side. Decoupling capacitors: RF side: 100 pF-10 nF, placed within 2 mm of the IC power pins. Value selected for the RF operating frequency. Avoid X5R/X7R capacitors near RF circuits (piezoelectric noise). Use NP0/C0G dielectric for RF decoupling. Digital side: 100 nF, 10 nF, 1 nF multi-value decoupling for broadband impedance. Bulk capacitors (10-100 μF) for low-frequency transients. (3) Ground strategy: single ground plane (preferred): use one continuous ground plane for both RF and digital. Never split the ground plane (creates radiating slots and ground loops). Use ground stitching vias to maintain low-impedance ground between RF and digital. Isolate the return current paths: route digital signals away from the RF section so their return currents do not flow under the RF circuits.
Category: Signal Integrity and High Speed Digital
Updated: April 2026
Product Tie-In: PCB Materials, Shielding, Capacitors

Mixed-Signal PDN Design

The PDN is the hidden pathway for digital noise to couple into RF circuits, and its design is one of the most critical aspects of mixed-signal PCB layout.

PDN Impedance Target

(1) The PDN impedance target is: Z_target = ΔV_allowed / I_transient. For an RF VCO supply with ΔV_allowed = 1 mV (to maintain phase noise) and I_transient = 10 mA: Z_target = 0.1 ohm. This target must be met from DC to the clock frequency. (2) The PDN impedance is shaped by: VRM (Voltage Regulator Module): provides low Z from DC to approximately 1 kHz. Bulk capacitors (10-100 μF): low Z from 1 kHz to 1 MHz. Decoupling capacitors (100 nF-10 nF): low Z from 1 MHz to 100 MHz. Power/ground plane capacitance: low Z from 100 MHz to 1 GHz. On-die capacitance: low Z above 1 GHz. Each stage must overlap in frequency to avoid resonant peaks in the PDN impedance.

PDN Design Rules
Z_target = ΔV / I_transient
LDO PSRR: 40-70 dB below 1 MHz
Ferrite bead: 10-30 dB isolation at 100 MHz-1 GHz
RF decoupling: NP0/C0G, 100 pF-10 nF
Single ground plane: no splits
Common Questions

Frequently Asked Questions

Can I use a switching regulator for RF power?

Only with significant filtering. A switching regulator (buck converter): generates switching noise at the switching frequency (1-5 MHz) and its harmonics. Noise level: -40 to -60 dBm at the switching frequency (10-100 mV ripple). RF circuits need: < 1 mV noise at the operating frequency. Solution: switcher → ferrite bead → LDO → RF circuit. The LDO post-regulation provides the clean supply. Cost: an additional $0.30-1.00 per LDO.

How many decoupling capacitors do I need?

Per RF IC power pin: 2-3 capacitors (e.g., 100 pF + 10 nF + 100 nF). Place the smallest value closest to the pin (it is effective at the highest frequency). Per digital IC: depends on the current transients. High-current FPGAs: 50-200 decoupling capacitors (specified in the vendor power integrity guide). Follow the IC manufacturer PDN recommendation (they provide specific capacitor values, quantities, and placement guidelines).

What is simultaneous switching noise (SSN)?

SSN occurs when multiple digital output pins switch simultaneously. Each switching pin: draws a current transient (10-50 mA per pin, with 0.5-1 ns rise time). For 100 pins switching simultaneously: total transient current = 1-5 A. This transient: flows through the PDN and ground plane inductance, creating a voltage spike (V = L × dI/dt). With L = 100 pH and dI/dt = 5A/1ns: V = 500 mV. This 500 mV spike on the ground or power rail can couple to the RF circuits through the shared ground plane.

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