What is the clock phase noise requirement for an ADC sampling at multi-GHz rates?
ADC Clock Jitter
Phase noise integration: to convert phase noise (dBc/Hz) to RMS jitter, integrate the phase noise spectrum from the offset frequency band of interest: σ_t = (1/(2π·f_carrier)) × √(2 × ∫L(f)df). For a clock at 1 GHz with -150 dBc/Hz flat phase noise from 1 kHz to 100 MHz: integrated jitter ≈ 90 fs. Most of the jitter contribution comes from the wideband noise floor (high offset frequencies), so the wideband phase noise of the clock source is more important than the close-in phase noise for ADC applications.
| Parameter | Pipeline ADC | SAR ADC | Sigma-Delta ADC |
|---|---|---|---|
| Sample Rate | 100 MS/s - 10 GS/s | 1-100 MS/s | 10 kS/s - 50 MS/s |
| Resolution | 8-14 bits | 10-20 bits | 16-24 bits |
| Latency | Several clock cycles | 1 conversion cycle | Many cycles (decimation) |
| Power | High | Low-moderate | Low |
| Typical RF Use | Direct sampling, DPD | Control, monitoring | Audio, baseband |
- Performance verification: confirm specifications against the application requirements before finalizing the design
- Environmental factors: temperature range, humidity, and vibration affect long-term reliability and parameter drift
- Cost vs. performance: evaluate whether the application demands premium components or standard commercial grades
- Interface compatibility: verify impedance, connector type, and mechanical form factor match the system architecture
Frequently Asked Questions
Which clock source is best for ADCs?
For lowest jitter: a fixed-frequency crystal oscillator (VCXO or OCXO) provides 10-50 fs RMS. For tunable clocks: a PLL-based synthesizer with a wideband loop bandwidth and low-noise VCO. Clean up the synthesizer output with a narrowband bandpass filter to reduce wideband noise. Dedicated ADC clock ICs (TI LMK04828, ADI HMC7044) provide multiple synchronized outputs with < 100 fs jitter.
Does jitter matter for baseband ADCs?
Less so. At f_in = 10 MHz: even 1 ps of jitter gives SNR = 84 dB (13.7 ENOB). At f_in = 100 MHz: 1 ps gives 64 dB (10.3 ENOB). Jitter becomes the dominant limitation at GHz input frequencies where sub-100 fs jitter is essential.