Digital and Mixed Signal RF ADC and DAC for RF Informational

How does the ENOB of an ADC degrade at higher input frequencies?

The effective number of bits (ENOB) of an ADC decreases as the input frequency increases due to: aperture jitter (timing uncertainty in the sample instant causes amplitude errors proportional to the signal slew rate), track-and-hold bandwidth (the T/H amplifier gain rolls off at high frequencies, reducing effective resolution), and comparator metastability (at higher speeds, the comparator has less settling time). The jitter-limited SNR is: SNR_jitter = -20·log10(2π × f_in × t_jitter). For 100 fs jitter at 1 GHz input: SNR = 64 dB (10.3 ENOB). At 5 GHz: SNR = 50 dB (7.8 ENOB). A 14-bit ADC may have 12 ENOB at low frequency but only 8-9 ENOB at its maximum input frequency. Always check the ENOB vs. frequency curve in the data sheet.
Category: Digital and Mixed Signal RF
Updated: April 2026
Product Tie-In: ADCs, DACs, Clock Sources

ENOB vs. Frequency

The total SNR combines quantization noise, thermal noise, aperture jitter, and harmonic distortion: SNR_total ≈ -10·log10(10^(-SNR_quant/10) + 10^(-SNR_thermal/10) + 10^(-SNR_jitter/10)). At low frequencies: quantization noise dominates and ENOB approaches the ideal value. At high frequencies: jitter dominates and ENOB degrades. The crossover point depends on the ADC's clock jitter specification and resolution.

ParameterPipeline ADCSAR ADCSigma-Delta ADC
Sample Rate100 MS/s - 10 GS/s1-100 MS/s10 kS/s - 50 MS/s
Resolution8-14 bits10-20 bits16-24 bits
LatencySeveral clock cycles1 conversion cycleMany cycles (decimation)
PowerHighLow-moderateLow
Typical RF UseDirect sampling, DPDControl, monitoringAudio, baseband
  • Performance verification: confirm specifications against the application requirements before finalizing the design
  • Environmental factors: temperature range, humidity, and vibration affect long-term reliability and parameter drift
  • Cost vs. performance: evaluate whether the application demands premium components or standard commercial grades
Common Questions

Frequently Asked Questions

How do I minimize ENOB degradation?

Use a low-jitter clock source (< 100 fs RMS for multi-GHz ADCs). Use a dedicated clock buffer/driver with low additive jitter. Keep the clock path short and impedance-matched. Use a bandpass filter before the ADC to limit the input bandwidth and reduce noise folding. Some ADCs have an internal clock divider that can reduce the effective jitter.

Is ENOB the same as SINAD?

ENOB is calculated from SINAD: ENOB = (SINAD - 1.76) / 6.02. SINAD (signal-to-noise-and-distortion ratio) includes all noise and distortion. A higher SINAD means more ENOB. At the ADC's specified maximum input frequency, the data sheet ENOB is typically 1-3 bits below the nominal resolution.

Need expert RF components?

Request a Quote

RF Essentials supplies precision components for noise-critical, high-linearity, and impedance-matched systems.

Get in Touch