Semiconductor and Device Technology III-V Semiconductors Informational

How do I select the right foundry process for a custom MMIC design?

Selecting the right foundry process for a custom MMIC (Monolithic Microwave Integrated Circuit) requires matching the circuit requirements to the process capabilities: (1) Frequency determines the technology node: DC to 6 GHz: GaAs HBT (0.5-2 um) or Si CMOS/SOI. Mature, low cost, high yield. 6-18 GHz: GaAs pHEMT (150-250 nm). The workhorse for X-band and Ku-band amplifiers. 18-40 GHz: GaAs pHEMT (100-150 nm) or mHEMT (100 nm). Higher fT is needed for adequate gain. 40-100 GHz: InP HEMT (50-100 nm) or mHEMT (50-70 nm) for LNAs. GaN (100 nm) for PAs. Above 100 GHz: InP HEMT (25-50 nm) or InP HBT. (2) Function determines the device type: PA: GaN HEMT (for power), GaAs HBT (for low/moderate power), or InP HBT (for above 100 GHz). LNA: GaAs pHEMT or mHEMT (for lowest noise at moderate frequencies), InP HEMT (for lowest noise at the highest frequencies). Switch: GaAs pHEMT (for high-linearity RF switches), SOI CMOS (for integrated switch + LNA/PA). Mixer/multiplier: GaAs pHEMT or InP HEMT (for low conversion loss and wide bandwidth). VCO/oscillator: GaAs HBT (low 1/f noise for low phase noise VCOs), InP HBT (for mmWave VCOs). (3) Output power determines the voltage and device size: < 1 W: GaAs HBT or pHEMT (5-12 V supply). 1-10 W: GaN HEMT (28 V supply). 10-100+ W: GaN HEMT on SiC (28-50 V supply). (4) Integration level: simple MMIC (single function: LNA, PA, mixer): any III-V process. Complex MMIC (transceiver with digital control, memory): SiGe BiCMOS or CMOS (allows integration of analog + digital). Multi-function III-V MMIC (LNA + mixer + switch): GaAs pHEMT or BiFET process (combines HEMT and HBT on the same wafer).
Category: Semiconductor and Device Technology
Updated: April 2026
Product Tie-In: Transistors, MMICs, Evaluation Boards

MMIC Foundry Process Selection

The foundry process selection is one of the earliest and most consequential decisions in MMIC design. Changing the process after the design is started is extremely costly (complete redesign from scratch).

  • Performance verification: confirm specifications against the application requirements before finalizing the design
  • Environmental factors: temperature range, humidity, and vibration affect long-term reliability and parameter drift
  • Cost vs. performance: evaluate whether the application demands premium components or standard commercial grades
  • Interface compatibility: verify impedance, connector type, and mechanical form factor match the system architecture
  • Margin allocation: include sufficient design margin to account for manufacturing tolerances and aging effects
Common Questions

Frequently Asked Questions

How much does a custom MMIC cost?

NRE (non-recurring engineering, one-time design + fabrication cost): simple MMIC (1-2 stages, single function): $50,000-$150,000 (design) + $20,000-$50,000 (MPW fabrication) = $70,000-$200,000 total NRE. Complex MMIC (5+ stages, multifunction transceiver): $200,000-$1,000,000 (design) + $50,000-$200,000 (fabrication) = $250,000-$1,200,000 total NRE. Per-die production cost (at volume): 1 mm² GaAs die: $5-$15 per die at 10,000+ units. 4 mm² GaN die: $20-$100 per die (higher substrate cost). 1 mm² InP die: $20-$50 per die. ROI: for a production run of 10,000+ units: the per-die cost is typically 10-50× lower than buying off-the-shelf MMICs (which include the vendor margin and are designed for general use rather than optimized for your application).

What is a multi-project wafer (MPW)?

An MPW run combines multiple different MMIC designs from different customers onto a single wafer. Each customer receives a small number of die (10-100) from the shared wafer. Advantages: much lower cost than a full wafer run (share the fabrication cost with 5-20 other designs). Ideal for prototyping and small-volume production. Disadvantages: fixed schedule (MPW runs are offered 2-4× per year by most foundries). Limited die count (may not be enough for production). Limited process options (MPW runs are typically on the foundry standard process; customization is not available). MPW providers: MAFIC (France), CSC (UK), IMEC (Belgium), and some US programs (DARPA MPC). Typical cost: $5,000-$30,000 per design (for 1-4 mm² die area, 20-50 die).

Can I simulate before choosing a process?

Yes, preliminary simulation with generic models can guide the process selection: (1) Use a generic transistor model (e.g., ideal HEMT with specified fT, fmax, NF_min) in the circuit simulator (ADS, AWR). Set the model parameters to the values advertised by each candidate process. (2) Simulate the target circuit with each model. Compare: gain, NF, P_out, PAE, and bandwidth. The process that provides adequate performance with the most margin is the best choice. (3) After selecting the process: obtain the actual PDK and redo the simulation with the foundry models. The foundry model will include parasitic effects and realistic component behavior that the generic model missed. The performance may differ by 1-3 dB from the generic model (usually worse). (4) Layout: design the physical layout with the PDK rules. Run EM simulation on the layout. The EM simulation accounts for coupling, radiation, and interconnect effects. This is the final design verification before tape-out.

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