How do I select the right foundry process for a custom MMIC design?
MMIC Foundry Process Selection
The foundry process selection is one of the earliest and most consequential decisions in MMIC design. Changing the process after the design is started is extremely costly (complete redesign from scratch).
| Parameter | Option A | Option B | Option C |
|---|---|---|---|
| Performance | High | Medium | Low |
| Cost | High | Low | Medium |
| Complexity | High | Low | Medium |
| Bandwidth | Narrow | Wide | Moderate |
| Typical Use | Lab/military | Consumer | Industrial |
Technical Considerations
(1) The PDK contains: device models (nonlinear models for transistors, diode models, linear models for passives), layout cells (standard transistor layouts, via definitions, resistor and capacitor cells), design rules (minimum dimensions, spacing rules, layer definitions), and simulation examples (reference circuits with expected performance). (2) Evaluate the PDK by: designing a simple benchmark circuit (a single-stage amplifier at the target frequency) and verifying that the simulated performance is reasonable. Check the model validity range: the model may be verified only to a certain frequency (e.g., 40 GHz). Using the model beyond its verified range is risky. Verify that passive elements (MIM capacitors, thin-film resistors, spiral inductors) have models and are available in the process. Check the via and interconnect models: at mmWave, the via and interconnect parasitics are significant and must be modeled. (3) Model confidence: ask the foundry for measurement vs simulation correlation data. A well-characterized process should show < 1 dB agreement between modeled and measured gain, and < 3 dB for return loss, at the target frequency.
Performance Analysis
(1) Technical: does the process meet the frequency, power, and noise requirements? A process that barely meets the requirements (operating near fmax) is risky; the design margin is thin. Prefer a process with 2× the required fT/fmax. (2) Maturity: a mature process (in production for 5+ years) has: well-characterized models, known yield (> 70% for complex MMICs), established reliability data, and a large user base (more examples and reference designs available). An immature process (< 2 years in production) may have: model inaccuracies, lower yield, and unknown reliability. Use immature processes only when the performance requirement cannot be met by any mature process. (3) Availability: lead time for wafer fabrication: 8-16 weeks (typical for III-V foundries). Minimum order: 1-10 wafers (some foundries offer multi-project wafer runs that reduce the cost by sharing a wafer with other designs). MPW (multi-project wafer): $5,000-$50,000 per design (depending on the die area). Full wafer run: $20,000-$200,000 per wafer lot (depending on the process). (4) Support: design support (application engineers, design reviews, and DRC checks), test services (on-wafer probing, die testing), and packaging services (die attach, wire bond, and module assembly).
Design Guidelines
When evaluating select the right foundry process for a custom mmic design?, engineers must account for the specific requirements of their target application. The optimal choice depends on the frequency range, power level, environmental conditions, and cost constraints of the overall system design.
Implementation Notes
When evaluating select the right foundry process for a custom mmic design?, engineers must account for the specific requirements of their target application. The optimal choice depends on the frequency range, power level, environmental conditions, and cost constraints of the overall system design.
- Performance verification: confirm specifications against the application requirements before finalizing the design
- Environmental factors: temperature range, humidity, and vibration affect long-term reliability and parameter drift
- Cost vs. performance: evaluate whether the application demands premium components or standard commercial grades
- Interface compatibility: verify impedance, connector type, and mechanical form factor match the system architecture
- Margin allocation: include sufficient design margin to account for manufacturing tolerances and aging effects
Practical Applications
When evaluating select the right foundry process for a custom mmic design?, engineers must account for the specific requirements of their target application. The optimal choice depends on the frequency range, power level, environmental conditions, and cost constraints of the overall system design.
Frequently Asked Questions
How much does a custom MMIC cost?
NRE (non-recurring engineering, one-time design + fabrication cost): simple MMIC (1-2 stages, single function): $50,000-$150,000 (design) + $20,000-$50,000 (MPW fabrication) = $70,000-$200,000 total NRE. Complex MMIC (5+ stages, multifunction transceiver): $200,000-$1,000,000 (design) + $50,000-$200,000 (fabrication) = $250,000-$1,200,000 total NRE. Per-die production cost (at volume): 1 mm² GaAs die: $5-$15 per die at 10,000+ units. 4 mm² GaN die: $20-$100 per die (higher substrate cost). 1 mm² InP die: $20-$50 per die. ROI: for a production run of 10,000+ units: the per-die cost is typically 10-50× lower than buying off-the-shelf MMICs (which include the vendor margin and are designed for general use rather than optimized for your application).
What is a multi-project wafer (MPW)?
An MPW run combines multiple different MMIC designs from different customers onto a single wafer. Each customer receives a small number of die (10-100) from the shared wafer. Advantages: much lower cost than a full wafer run (share the fabrication cost with 5-20 other designs). Ideal for prototyping and small-volume production. Disadvantages: fixed schedule (MPW runs are offered 2-4× per year by most foundries). Limited die count (may not be enough for production). Limited process options (MPW runs are typically on the foundry standard process; customization is not available). MPW providers: MAFIC (France), CSC (UK), IMEC (Belgium), and some US programs (DARPA MPC). Typical cost: $5,000-$30,000 per design (for 1-4 mm² die area, 20-50 die).
Can I simulate before choosing a process?
Yes, preliminary simulation with generic models can guide the process selection: (1) Use a generic transistor model (e.g., ideal HEMT with specified fT, fmax, NF_min) in the circuit simulator (ADS, AWR). Set the model parameters to the values advertised by each candidate process. (2) Simulate the target circuit with each model. Compare: gain, NF, P_out, PAE, and bandwidth. The process that provides adequate performance with the most margin is the best choice. (3) After selecting the process: obtain the actual PDK and redo the simulation with the foundry models. The foundry model will include parasitic effects and realistic component behavior that the generic model missed. The performance may differ by 1-3 dB from the generic model (usually worse). (4) Layout: design the physical layout with the PDK rules. Run EM simulation on the layout. The EM simulation accounts for coupling, radiation, and interconnect effects. This is the final design verification before tape-out.