How do I calculate the quantization noise floor of an ADC in dBFS per Hz?
Quantization Noise
The total quantization noise power of an N-bit ADC is: P_quant = (V_FSR²)/(12 × 2^(2N)), where V_FSR is the full-scale range. In dBFS: the total quantization noise = -(6.02N + 1.76) dBFS. This noise is assumed uniformly distributed from DC to f_s/2. The noise spectral density is obtained by dividing by the Nyquist bandwidth: PSD = -(6.02N + 1.76) - 10·log10(f_s/2) dBFS/Hz.
| Parameter | Pipeline ADC | SAR ADC | Sigma-Delta ADC |
|---|---|---|---|
| Sample Rate | 100 MS/s - 10 GS/s | 1-100 MS/s | 10 kS/s - 50 MS/s |
| Resolution | 8-14 bits | 10-20 bits | 16-24 bits |
| Latency | Several clock cycles | 1 conversion cycle | Many cycles (decimation) |
| Power | High | Low-moderate | Low |
| Typical RF Use | Direct sampling, DPD | Control, monitoring | Audio, baseband |
- Performance verification: confirm specifications against the application requirements before finalizing the design
- Environmental factors: temperature range, humidity, and vibration affect long-term reliability and parameter drift
- Cost vs. performance: evaluate whether the application demands premium components or standard commercial grades
Frequently Asked Questions
What is process gain?
Process gain is the SNR improvement obtained by digitally filtering a wideband ADC output to a narrower bandwidth: PG = 10·log10(f_s / (2×B)). For a 1 GSPS ADC with a 1 MHz signal bandwidth: PG = 10·log10(500M/1M) = 27 dB. This 27 dB of process gain effectively adds 4.5 bits of resolution for the narrowband signal.
Does this apply to real ADCs?
The quantization noise formula gives the ideal floor. Real ADC noise includes thermal noise from the input buffer, aperture jitter noise, and harmonic distortion. The actual noise floor is typically 5-15 dB higher than the ideal quantization noise floor, which is why ENOB is always less than the nominal bit count.