How is clock recovery implemented in coherent optical receivers?

In coherent receivers for 100G to 800G, clock recovery is fully digital, implemented in the DSP ASIC after the ADC. The ADC runs from a free-running local oscillator at approximately the baud rate (28 to 130 GBaud). The DSP uses a timing error detector, typically Mueller-Muller for baud-rate sampling or Gardner for 2x oversampling, to estimate the sampling phase error. This error drives a digital loop filter that adjusts either a numerically controlled oscillator (NCO) for interpolation-based resampling or the ADC clock frequency directly via a small DAC. The loop bandwidth is typically 100 kHz to 4 MHz, balancing jitter tracking against noise. Digital implementation enables adaptive algorithms that can also compensate for chromatic dispersion and PMD simultaneously.

Optical & Photonic RF

Clock Recovery (Optical)

Q: How does a bang-bang CDR differ from a linear CDR?

A linear CDR uses an analog phase detector (such as a Hogge or Alexander detector) that produces an error signal proportional to the phase difference between data transitions and the sampling clock. This allows precise phase tracking but requires analog multipliers operating at the full data rate. A bang-bang (binary) CDR quantizes the phase error to just early or late (plus or minus 1), simplifying the phase detector to a few flip-flops but introducing limit-cycle jitter (bang-bang jitter) of typically 2 to 5% UI peak-to-peak. Bang-bang CDRs dominate in high-speed designs (25G and above) because the simple digital phase detector scales easily to 56 GBaud and beyond in advanced CMOS, while the proportional path is added separately for improved jitter performance.

Q: What jitter tolerance is required for optical CDR?

ITU-T G.8251 and IEEE 802.3 define jitter tolerance masks that specify the minimum sinusoidal jitter amplitude the CDR must track without increasing BER, as a function of jitter frequency. At low frequencies (below 10 Hz for OTN), the CDR must tolerate 15 UI peak-to-peak of wander. At mid frequencies (10 Hz to 4 MHz), tolerance follows a 1/f slope from 15 UI down to 0.15 UI. Above the jitter transfer bandwidth (4 to 10 MHz), the CDR is no longer expected to track and tolerance flattens at 0.15 UI. For 100G Ethernet (IEEE 802.3ba), the high-frequency tolerance floor is 0.1 UI at frequencies above 4 MHz, with the mask extending to half the baud rate.

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Clock recovery in optical communications is the process of extracting a timing reference from an incoming data stream to regenerate the sampling clock for bit decisions. CDR circuits use PLL-based or bang-bang phase detector architectures to lock onto data transitions at rates from 10G to 800G. In modern coherent receivers, CDR is fully digital, using Mueller-Muller or Gardner timing error detectors in the DSP. Key specifications include jitter tolerance (0.15 to 1.5 UI), jitter transfer bandwidth (4 to 10 MHz for OTN), and acquisition time (under 10 ms).

Category: Optical & Photonic RF

Data rates: 10G to 800G

Standard: ITU-T G.8251, IEEE 802.3

Understanding Clock Recovery (Optical)

Unlike RF wireless links where the receiver typically has an independent frequency reference (GPS-disciplined oscillator or base station timing), optical fiber links embed the clock in the data stream itself. The receiver must extract this clock from the data transitions to know precisely when to sample each bit. In NRZ (non-return-to-zero) modulation, clock content depends on the data pattern: long runs of consecutive identical digits (CID) contain no transitions, so the CDR must maintain frequency accuracy from its own VCO/oscillator during these gaps. Line coding (8B/10B, 64B/66B) guarantees a minimum transition density to keep the CDR locked.

The CDR's loop bandwidth represents a fundamental tradeoff. A wider bandwidth tracks input jitter better (higher jitter tolerance) but also transfers more jitter through the regenerator chain, potentially accumulating jitter across multiple spans. ITU-T G.8251 specifies maximum jitter transfer bandwidth to prevent this accumulation: 10 MHz for STM-64/OC-192 (10G) and 4 MHz for OTU4 (100G). The CDR's jitter generation, measured as random jitter (RJ) and deterministic jitter (DJ), must also meet tight limits. For 100G per lane (53 GBaud PAM4), the total CDR jitter budget is typically 0.1 UI RMS random plus 0.05 UI deterministic, leaving margin for channel, transmitter, and crosstalk jitter components.

CDR Timing Equations

Mueller-Muller Timing Error:
e(n) = x(n) × d(n-1) - x(n-1) × d(n)

CDR Loop Transfer Function:
H(s) = (2ζω_ns + ω_n²) / (s² + 2ζω_ns + ω_n²)

Jitter Transfer Bandwidth:
f_-3dB = ω_n/(2π) × √(1 + 2ζ² + √(1 + (2ζ²)²))

Where x(n) = sampled data value, d(n) = detected symbol, ζ = damping factor (typically 0.7 to 1.0), ω_n = loop natural frequency. Second-order PLL with ζ = 0.707 gives f_-3dB ≈ 2.06 × f_n.

CDR Architecture Comparison

Architecture	Data Rate	Phase Detector	Jitter (RMS)	Application
Analog PLL (Hogge)	1G to 10G	Linear, proportional	<0.5% UI	SONET/SDH regenerators
Bang-bang (Alexander)	10G to 56G	Binary (early/late)	2 to 5% UI	High-speed SerDes, NRZ
Half-rate bang-bang	25G to 112G	Binary at half rate	1.5 to 3% UI	PAM4 transceivers
Digital (Mueller-Muller)	100G to 800G	Baud-rate, DSP-based	<0.3% UI	Coherent receivers
Oversampling (Gardner)	10G to 400G	2x oversampled digital	<0.5% UI	Burst-mode PON, FlexO

Common Questions

Frequently Asked Questions

How does a bang-bang CDR differ from a linear CDR?

A linear CDR uses a phase detector that produces error proportional to phase difference, allowing precise tracking but requiring analog circuits at full data rate. A bang-bang CDR quantizes phase error to early/late, simplifying the detector to a few flip-flops but introducing limit-cycle jitter of 2 to 5% UI. Bang-bang designs dominate above 25G because the simple digital detector scales easily to 56 GBaud and beyond in CMOS.

What jitter tolerance is required for optical CDR?

ITU-T G.8251 and IEEE 802.3 define masks specifying minimum tolerable sinusoidal jitter versus frequency. Below 10 Hz, 15 UI of wander must be tracked. From 10 Hz to 4 MHz, tolerance follows a 1/f slope down to 0.15 UI. Above the jitter transfer bandwidth (4 to 10 MHz), tolerance flattens at 0.15 UI. For 100G Ethernet, the high-frequency floor is 0.1 UI above 4 MHz.

How is CDR implemented in coherent optical receivers?

In coherent 100G to 800G receivers, CDR is fully digital in the DSP. The ADC runs from a free-running oscillator at approximately the baud rate. Mueller-Muller (baud-rate) or Gardner (2x oversampled) timing error detectors estimate sampling phase error, driving a digital loop filter that adjusts an NCO for interpolation-based resampling. Loop bandwidth is 100 kHz to 4 MHz, balancing jitter tracking against noise.

Related Terms

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