Signal Integrity

Jitter

/jit-er/
Jitter is the short-term variation in the timing of a periodic signal from its ideal position. It is the time-domain equivalent of phase noise. In ADCs, clock jitter directly limits the achievable SNR: SNR = -20 log(2 pi f_input x t_jitter_rms). At 5 GHz input, even 100 fs of jitter limits SNR to 50 dB. Jitter comes from oscillator phase noise, power supply noise, and substrate coupling.
Category: Signal Integrity
Related to: Phase Noise, ADC, Clock, SNR
Units: ps (rms), fs (rms)

Understanding Jitter

Jitter is critical for high-speed data converters, digital communications, and synchronization systems. Every clock edge has uncertainty in its exact timing position. This uncertainty causes sampling errors in ADCs, bit errors in serial links, and timing violations in digital circuits.

Jitter Types

  • Random jitter (RJ): Gaussian-distributed, unbounded. From thermal noise and phase noise. Measured as RMS value.
  • Deterministic jitter (DJ): Bounded, systematic. From intersymbol interference, crosstalk, and periodic noise sources.
  • Total jitter (TJ): TJ = DJ + 2 x N x RJ (at BER = 10^-N). Combines random and deterministic components.

Jitter Impact on ADCs

Clock jitter causes the ADC to sample at slightly wrong times. For a sinusoidal input at frequency f_in, the resulting noise from jitter is: SNR_jitter = -20 log(2 pi f_in x t_j). This becomes the dominant SNR limitation at high input frequencies.

Jitter-limited SNR:
SNR = -20 log(2 pi f_input x t_jitter_rms)

Examples (100 fs jitter):
100 MHz input: SNR = 70 dB
1 GHz input: SNR = 50 dB
5 GHz input: SNR = 36 dB
10 GHz input: SNR = 30 dB

Clock jitter sources:
Crystal oscillator: 50-200 fs
PLL synthesizer: 100 fs - 1 ps
VCO free-running: 500 fs - 5 ps
Common Questions

Frequently Asked Questions

What is jitter?

Jitter is the variation in timing of periodic signal edges from their ideal positions. It is the time-domain manifestation of phase noise. Sources include oscillator phase noise, power supply noise, and electromagnetic coupling. It is measured in picoseconds or femtoseconds RMS.

Why does jitter matter for ADCs?

ADC clock jitter causes sampling at wrong times, converting timing errors to amplitude errors. The resulting SNR = -20log(2 pi f_in x jitter). At GHz input frequencies, even 100 femtoseconds of jitter significantly limits dynamic range.

How is jitter related to phase noise?

Jitter and phase noise are the same phenomenon in different domains. Jitter is the time-domain view (timing uncertainty); phase noise is the frequency-domain view (spectral spreading). They are related by: jitter_rms = sqrt(2 x integral(L(f) df)).

Signal Integrity

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