Clock EMI
Understanding Clock EMI
Digital clocks are the single largest contributor to electromagnetic emissions in nearly every electronic product. Unlike random data signals whose energy spreads across a continuous spectrum, clock signals are perfectly periodic, concentrating all their spectral energy at discrete harmonics of the fundamental frequency. A trapezoidal clock waveform has an amplitude envelope that follows two breakpoints: the first at 1/(π × τ) where τ is the pulse width (flat spectrum below this), and the second at 1/(π × tr) where tr is the rise/fall time (spectrum rolls off at -20 dB/decade above this). For a 100 MHz clock with 50% duty cycle and 0.5 ns rise time, the second breakpoint is at 637 MHz, meaning harmonics up to the 6th are at nearly full amplitude.
The radiation efficiency of clock traces depends on their electrical length relative to wavelength. A 5 cm microstrip trace becomes a quarter-wave monopole at about 1 GHz (accounting for the effective dielectric constant of FR-4), and its radiation efficiency peaks near this frequency. Even modest clock amplitudes (3.3V LVCMOS) produce field strengths of 40 to 60 dBμV/m at 3 meters at resonant harmonics, often exceeding Cispr 32 Class B limits by 10 to 20 dB. Effective mitigation combines source control (slower edges, spread spectrum), path control (stripline routing, ground planes, series termination), and receptor shielding (board-level shields, filtered connectors).
Clock EMI Equations
An = (2Vτ/T) × |sinc(nπτ/T)| × |sinc(nπtr/T)|
Maximum Significant Frequency:
fmax = 1/(π × tr) (bandwidth of emissions)
SSCG Peak Reduction:
ΔE = 20log(δf / RBW) dB (for δf > RBW)
Where V = amplitude, τ = pulse width, T = period, tr = rise time, n = harmonic number, δf = frequency deviation, RBW = receiver resolution bandwidth (120 kHz for CISPR). Example: 100 MHz, 1% spread, RBW = 120 kHz gives ΔE ≈ 18 dB.
Clock EMI Mitigation Techniques
| Technique | Reduction | Complexity | Impact on Signal | Best For |
|---|---|---|---|---|
| Spread spectrum (SSCG) | 6 to 18 dB | Low (IC swap) | 0.5 to 1.5% jitter added | Display, USB, PCIe clocks |
| Slew rate control | 3 to 10 dB | Low | Reduced timing margin | Non-critical clock nets |
| Series source termination | 6 to 12 dB | Low (resistor) | Minimal if matched | All clock outputs |
| Stripline routing | 15 to 25 dB | Medium (layer stack) | Higher loss, more vias | High-speed clocks >200 MHz |
| Board-level shield | 20 to 40 dB | High (mechanical) | Thermal, rework access | Final compliance fix |
Frequently Asked Questions
Why are clock signals the biggest EMI source?
Clock signals are periodic with fast edges, concentrating energy at discrete harmonic frequencies rather than spreading it across a continuous band. A 100 MHz clock with 0.5 ns rise time on a 5 cm trace acts as a quarter-wave antenna at 1.5 GHz, radiating efficiently at its 15th harmonic. Even 3.3V LVCMOS clocks produce 40 to 60 dBμV/m at 3 meters near the trace's resonant frequency.
How does spread spectrum clocking reduce EMI?
SSCG frequency-modulates the clock by 0.5 to 1.5% using a triangular or Hershey-kiss profile at 30 to 60 kHz. This spreads each harmonic from a narrow spike into a wider band, reducing peak amplitude in the EMI receiver's 120 kHz resolution bandwidth. For 1% spread on a 100 MHz clock, the reduction is approximately 20log(1000/120) = 18 dB at the fundamental.
What PCB layout practices minimize clock EMI?
Route clocks on inner stripline layers between solid ground planes. Keep traces under λ/20 at the highest significant harmonic. Use 22 to 47 Ω series source termination at the driver. Place 100 nF plus 1 nF decoupling within 3 mm of clock driver VCC pins. Avoid routing near board edges, connectors, or ground plane gaps. Use the slowest rise time that meets setup/hold timing.