Digital and Mixed Signal RF Digital Signal Processing for RF Informational

How do I implement a digital phase locked loop for carrier recovery in a digital receiver?

Q: How does frequency offset affect the PLL?

The maximum frequency offset the DPLL can acquire is limited by the pull-in range: f_pull ≈ 2*pi*B_n*sqrt(2*zeta) for a second-order loop. For B_n = 0.01 × symbol rate and 10 MBaud: f_pull ≈ 90 kHz. Frequency offsets beyond this range require a separate acquisition aid: (1) Frequency discriminator (AFC): computes frequency error from the derivative of the phase (e.g., conjugate-multiply successive symbols and take the argument). The AFC has a wider capture range but poorer noise performance. (2) FFT-based frequency estimation: compute the FFT of the M-th power signal and find the spectral peak. Accurate to ±f_FFT_resolution = f_s/N_FFT. For N_FFT = 1024 at 10 MHz symbol rate: resolution = 9.77 kHz. Cascade: AFC (coarse, ±500 kHz range) → PLL (fine, ±90 kHz) for robust acquisition under large frequency uncertainty.

Q: What is cycle slipping and how do I prevent it?

Cycle slipping occurs when the PLL phase error momentarily exceeds ±pi, causing the loop to slip one or more carrier cycles. This produces a burst of bit errors (the constellation rotates by 90° or 180° for QPSK). Causes: low SNR (noise pushes the phase error beyond pi), rapid phase changes (step or ramp phase disturbances exceeding the loop tracking capability), and narrow loop bandwidth (slow response to rapid phase changes). Prevention: (1) Select B_n wide enough to track expected phase perturbations (oscillator phase noise, fading). (2) Use differential encoding (DQPSK instead of QPSK) to limit errors from a cycle slip to 2-4 bits instead of continuous. (3) Implement cycle-slip detection: monitor the integrator output for sudden jumps exceeding pi; if detected, reset or re-acquire. (4) Use a third-order loop for tracking frequency ramps (Doppler) without steady-state phase error.

Q: Can the DPLL track phase noise from the local oscillator?

Yes, within its loop bandwidth. Phase noise within B_n is tracked and removed. Phase noise beyond B_n passes through and appears as residual phase error on the demodulated constellation. For a local oscillator with phase noise L(f) = -100 dBc/Hz at 10 kHz offset and a DPLL with B_n = 5 kHz: phase noise from 0-5 kHz is tracked (removed), phase noise from 5 kHz onwards contributes to residual phase error. The residual phase noise variance: sigma_phi^2 = 2 × integral(10^(L(f)/10) df, from B_n to f_s/2). For L(f) = -100 dBc/Hz flat from 5 kHz to 5 MHz: sigma_phi^2 = 2 × 10^-10 × 5×10^6 = 10^-3 rad^2. EVM contribution: sqrt(10^-3) ≈ 0.032 rad ≈ 1.8° ≈ -35 dB EVM. Adequate for 64-QAM but marginal for 256-QAM.

A digital phase locked loop (DPLL) for carrier recovery tracks and removes the residual carrier frequency and phase offset in a digitally demodulated signal. The DPLL consists of: (1) Phase detector: extracts the phase error between the received signal and the local estimate. For BPSK/QPSK: a decision-directed phase detector computes the error as e[n] = Im(y[n] × conj(d[n])), where y[n] is the received symbol and d[n] is the nearest constellation point. For higher-order QAM: use a data-aided or blind phase error detector. (2) Loop filter: typically a proportional-integral (PI) filter: F(z) = K_p + K_i/(1-z^-1), where K_p controls the proportional response (acquisition speed) and K_i controls the integral response (steady-state tracking accuracy). The output of the loop filter is the frequency correction. (3) NCO (Numerically Controlled Oscillator): accumulates the frequency correction to produce the instantaneous phase estimate: phi[n+1] = phi[n] + freq[n]. The NCO generates cos(phi) and sin(phi) using CORDIC or a lookup table. (4) Complex rotator: multiplies the received signal by exp(-j×phi[n]) to remove the estimated phase, producing the corrected output. Loop bandwidth selection: B_n = (K_p^2 + 2*K_i*K_p) / (4*(K_p + K_i)) for a second-order loop. Typical B_n: 0.1-1% of the symbol rate (e.g., 1-10 kHz for a 1 MBaud signal). Narrower B_n provides better noise rejection but slower acquisition. For burst-mode receivers: wider initial B_n (1-5% of symbol rate) for fast acquisition, then narrow for tracking.

Category: Digital and Mixed Signal RF

Updated: April 2026

Product Tie-In: FPGAs, SDR Platforms, DSP Modules

Digital Carrier Recovery PLL

Carrier recovery is essential in any coherent digital receiver because the transmitter and receiver oscillators are never perfectly aligned in frequency and phase. The DPLL continuously tracks and corrects for these offsets, enabling reliable demodulation.

Parameter	Pipeline ADC	SAR ADC	Sigma-Delta ADC
Sample Rate	100 MS/s - 10 GS/s	1-100 MS/s	10 kS/s - 50 MS/s
Resolution	8-14 bits	10-20 bits	16-24 bits
Latency	Several clock cycles	1 conversion cycle	Many cycles (decimation)
Power	High	Low-moderate	Low
Typical RF Use	Direct sampling, DPD	Control, monitoring	Audio, baseband

Sampling and Quantization

The DPLL is a sampled-data control system with dynamics governed by the loop bandwidth B_n and damping factor zeta. Second-order loop (PI filter): the closed-loop transfer function is H(z) = (K_p*z + K_i - K_p) / (z^2 + (K_p-2)*z + (1-K_p+K_i)). For stability: K_p < 2 and K_i < K_p. Damping factor: zeta = 0.707 (critical damping) is standard for most applications. The natural frequency omega_n = sqrt(K_i) and zeta = K_p/(2*omega_n). Given target B_n and zeta, solve for K_p and K_i: K_i = (4*B_n*zeta/(zeta + 1/(4*zeta)))^2, K_p = 2*zeta*sqrt(K_i). For B_n = 0.01 (1% of symbol rate) and zeta = 0.707: K_i = 1.47×10^-4, K_p = 0.0172. These coefficients are implemented in fixed-point arithmetic on the FPGA, typically using 16-32 bit accumulators for the integrator to maintain sufficient frequency resolution.

Dynamic Range Considerations

(1) Decision-directed (DD): makes hard decisions on received symbols and uses the angle between the received and decided points as the error. Works after initial acquisition when the SNR is high enough for reliable decisions. Squaring loss: minimal at high SNR, increases at low SNR. (2) Costas loop (modified): for BPSK, computes error as e = I*Q (product of in-phase and quadrature). For QPSK: e = I*sign(Q) - Q*sign(I). Self-synchronizing (no decision required), but has a 90° phase ambiguity (QPSK) or 180° ambiguity (BPSK) that must be resolved by differential encoding or unique-word detection. (3) M-th power: for M-PSK, raise the signal to the M-th power to remove modulation, then track the M×f_carrier tone. Advantages: data-independent. Disadvantages: SNR penalty of 10*log10(M) dB and limited to PSK modulations. (4) Pilot-assisted: use known pilot symbols (embedded in the data stream) for unambiguous phase estimation. Used in OFDM (Wi-Fi, LTE) where scattered pilots enable per-subcarrier phase tracking.

Performance verification: confirm specifications against the application requirements before finalizing the design
Environmental factors: temperature range, humidity, and vibration affect long-term reliability and parameter drift
Cost vs. performance: evaluate whether the application demands premium components or standard commercial grades

Clock and Timing

The DPLL runs at the symbol rate (not the sample rate), reducing computation. For a 10 MBaud QPSK receiver: DPLL operates at 10 MHz. Resources: phase detector: 2-4 multipliers + comparator. Loop filter: 1-2 multipliers + accumulator (32-48 bit for frequency accuracy). NCO: 32-bit phase accumulator + CORDIC (8-16 stages, 8-16 multipliers) or LUT (1-4 kB ROM lookup table for sin/cos). Complex rotator: 4 multipliers + 2 adders. Total: 15-30 DSP blocks, <1% of a mid-range FPGA. For multi-carrier OFDM: a separate phase tracker per subcarrier or a polynomial phase model across subcarriers (pilot-interpolated) is used, implemented as a matrix-vector operation in the frequency domain. Acquisition performance: from cold start (unknown frequency offset up to ±100 kHz): the DPLL acquires lock within 50-200 symbols at B_n = 0.01, corresponding to 5-20 μs at 10 MBaud. For faster acquisition: use a frequency discriminator (AFC) loop for coarse correction before enabling the fine PLL.

Common Questions

Frequently Asked Questions

How does frequency offset affect the PLL?

The maximum frequency offset the DPLL can acquire is limited by the pull-in range: f_pull ≈ 2*pi*B_n*sqrt(2*zeta) for a second-order loop. For B_n = 0.01 × symbol rate and 10 MBaud: f_pull ≈ 90 kHz. Frequency offsets beyond this range require a separate acquisition aid: (1) Frequency discriminator (AFC): computes frequency error from the derivative of the phase (e.g., conjugate-multiply successive symbols and take the argument). The AFC has a wider capture range but poorer noise performance. (2) FFT-based frequency estimation: compute the FFT of the M-th power signal and find the spectral peak. Accurate to ±f_FFT_resolution = f_s/N_FFT. For N_FFT = 1024 at 10 MHz symbol rate: resolution = 9.77 kHz. Cascade: AFC (coarse, ±500 kHz range) → PLL (fine, ±90 kHz) for robust acquisition under large frequency uncertainty.

What is cycle slipping and how do I prevent it?

Cycle slipping occurs when the PLL phase error momentarily exceeds ±pi, causing the loop to slip one or more carrier cycles. This produces a burst of bit errors (the constellation rotates by 90° or 180° for QPSK). Causes: low SNR (noise pushes the phase error beyond pi), rapid phase changes (step or ramp phase disturbances exceeding the loop tracking capability), and narrow loop bandwidth (slow response to rapid phase changes). Prevention: (1) Select B_n wide enough to track expected phase perturbations (oscillator phase noise, fading). (2) Use differential encoding (DQPSK instead of QPSK) to limit errors from a cycle slip to 2-4 bits instead of continuous. (3) Implement cycle-slip detection: monitor the integrator output for sudden jumps exceeding pi; if detected, reset or re-acquire. (4) Use a third-order loop for tracking frequency ramps (Doppler) without steady-state phase error.

Can the DPLL track phase noise from the local oscillator?

Yes, within its loop bandwidth. Phase noise within B_n is tracked and removed. Phase noise beyond B_n passes through and appears as residual phase error on the demodulated constellation. For a local oscillator with phase noise L(f) = -100 dBc/Hz at 10 kHz offset and a DPLL with B_n = 5 kHz: phase noise from 0-5 kHz is tracked (removed), phase noise from 5 kHz onwards contributes to residual phase error. The residual phase noise variance: sigma_phi^2 = 2 × integral(10^(L(f)/10) df, from B_n to f_s/2). For L(f) = -100 dBc/Hz flat from 5 kHz to 5 MHz: sigma_phi^2 = 2 × 10^-10 × 5×10^6 = 10^-3 rad^2. EVM contribution: sqrt(10^-3) ≈ 0.032 rad ≈ 1.8° ≈ -35 dB EVM. Adequate for 64-QAM but marginal for 256-QAM.

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