How do I design a reference clock distribution for a multi-lane SerDes interface?

Designing a reference clock distribution for a multi-lane SerDes interface ensures that all SerDes lanes share a common, low-jitter reference clock with matched propagation delays. The reference clock is used by each lane's PLL (Phase-Locked Loop) to generate the high-speed serial clock (e.g., 156.25 MHz reference × 180 = 28.125 GHz for 56G PAM4 Ethernet). The design addresses: clock source (a low-jitter crystal oscillator or MEMS oscillator generates the reference clock; specifications: frequency: 100-156.25 MHz (common reference frequencies for PCIe and Ethernet), jitter: less than 0.2 ps RMS (12 kHz-20 MHz integration band) for 56G+ SerDes (every picosecond of reference clock jitter is multiplied by the PLL multiplication factor; for N=180: 0.1 ps RMS reference jitter → 18 ps RMS output jitter if not filtered)), clock distribution (the reference clock is distributed to all SerDes lanes via: a clock buffer/fanout IC (Silicon Labs Si5332, TI LMK05318, Renesas 8T49N242: these ICs take one reference clock input and produce multiple matched clock outputs with added jitter less than 100 fs RMS), or point-to-point traces from the source to each SerDes IC (used when the SerDes ICs have built-in clock recovery from the data stream, CDR, and only need a reference for frequency acquisition)), trace routing (the clock traces must be impedance-controlled (100 ohm differential for LVDS, 50 ohm single-ended for LVCMOS), matched in length to within ±5 ps between lanes (to minimize skew between SerDes lanes' PLL lock times and frequency offsets), and routed as far as possible from high-speed data lanes and switching power supplies (to minimize coupling of noise into the reference clock)).