Signal Integrity and High Speed Digital Additional SI Topics Informational

What is the package-board co-simulation methodology for a high speed digital IC?

The package-board co-simulation methodology for a high-speed digital IC simulates the IC's package interconnects and the PCB together as a unified system, capturing the electromagnetic coupling effects that are missed when the package and board are simulated separately. The methodology is necessary because at high frequencies (above approximately 1 GHz): the package's bond wires, substrate traces, and BGA balls interact electromagnetically with the PCB's traces, vias, and planes. These interactions include: impedance discontinuities at the package-board interface, resonances created by the combined package-board cavity, and crosstalk between package pins and adjacent PCB traces. The co-simulation flow: extract the package model (the IC vendor provides an S-parameter or SPICE model of the package; for high-performance ICs: the vendor provides a 3D EM model or a detailed broadband IBIS-AMI model), extract the PCB model (simulate the PCB layout (traces, vias, planes, connectors) using a 3D EM solver (Ansys HFSS, Cadence EMX, Keysight EMPro) or a 2.5D solver (Ansys SIwave, Cadence PowerSI) to generate S-parameters or RLGC models), combine the models (connect the package model outputs to the PCB model inputs at the BGA pad interface), and run time-domain or frequency-domain analysis (simulate the complete signal path from the IC's die pad through the package through the BGA through the PCB trace to the far-end connector or receiver). Tools: Ansys HFSS + SIwave + Circuit: the most common commercial workflow for package-board co-simulation. Cadence Sigrity: provides integrated package and board analysis. Keysight ADS + EMPro: circuit-EM co-simulation.

Category: Signal Integrity and High Speed Digital

Updated: April 2026

Product Tie-In: PCB Materials, Test Equipment

Package-Board Co-Simulation

Package-board co-simulation is essential for: high-speed serial links (PCIe Gen 5/6, 112G SerDes), DDR5 memory interfaces, and any signaling above 10 Gbps where the package discontinuity significantly impacts the channel performance.

Parameter	Option A	Option B	Option C
Performance	High	Medium	Low
Cost	High	Low	Medium
Complexity	High	Low	Medium
Bandwidth	Narrow	Wide	Moderate
Typical Use	Lab/military	Consumer	Industrial

Sampling and Quantization

When evaluating the package-board co-simulation methodology for a high speed digital ic?, engineers must account for the specific requirements of their target application. The optimal choice depends on the frequency range, power level, environmental conditions, and cost constraints of the overall system design.

Performance verification: confirm specifications against the application requirements before finalizing the design
Environmental factors: temperature range, humidity, and vibration affect long-term reliability and parameter drift
Cost vs. performance: evaluate whether the application demands premium components or standard commercial grades
Interface compatibility: verify impedance, connector type, and mechanical form factor match the system architecture

Dynamic Range Considerations

When evaluating the package-board co-simulation methodology for a high speed digital ic?, engineers must account for the specific requirements of their target application. The optimal choice depends on the frequency range, power level, environmental conditions, and cost constraints of the overall system design.

Common Questions

Frequently Asked Questions

When is co-simulation necessary?

Co-simulation is necessary for: data rates above approximately 10 Gbps (PCIe Gen 4+, 25G+ Ethernet), DDR5 and beyond (data rates of 3.2-8.4 GT/s where the channel budget is very tight), any design where the package model shows significant impedance discontinuities in the 1-10 GHz range, and designs that have failed signal integrity analysis with separate package and board models. For lower-speed designs (less than 5 Gbps): a simplified package model (lumped RLC) combined with a 2D transmission line model of the PCB traces is usually sufficient.

What package model format is used?

Common package model formats: S-parameter (.s2p, .snp): frequency-domain model. Most accurate but: can be large for packages with many ports (a 1000-ball BGA has thousands of ports). Touchstone 2.0 or generalized S-parameters. IBIS (Input/Output Buffer Information Specification): industry-standard behavioral model of the IC driver/receiver. IBIS-AMI: adds algorithmic modeling for equalization (CTLE, DFE, CDR). The AMI model captures the IC's signal processing. HSPICE subcircuit: SPICE-compatible model of the package interconnects. RLGC matrix: broadband transmission line parameters for each package trace. Best practice: use the S-parameter model for the package's passive interconnects, combined with the IBIS-AMI model for the IC's active driver/receiver behavior.

How do I get the package model?

IC vendors: major IC vendors (Intel, AMD, Nvidia, TI, Broadcom) provide package models for their high-speed ICs. The model is typically available under NDA or through the vendor's design support portal. Model types: basic IBIS model (available for most ICs; adequate for low-speed designs), IBIS-AMI model (available for high-speed SerDes ICs; essential for channel simulation), S-parameter model of the package (available for high-speed ICs; used for co-simulation), and HFSS/CST 3D model (available for premium ICs under NDA; the most detailed model for accurate co-simulation). If the vendor does not provide a package model: approximate the package using a generic BGA model with estimated parasitics (0.5-1.5 nH per BGA ball, 0.1-0.3 pF per pad).

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