What is the package-board co-simulation methodology for a high speed digital IC?

The package-board co-simulation methodology for a high-speed digital IC simulates the IC's package interconnects and the PCB together as a unified system, capturing the electromagnetic coupling effects that are missed when the package and board are simulated separately. The methodology is necessary because at high frequencies (above approximately 1 GHz): the package's bond wires, substrate traces, and BGA balls interact electromagnetically with the PCB's traces, vias, and planes. These interactions include: impedance discontinuities at the package-board interface, resonances created by the combined package-board cavity, and crosstalk between package pins and adjacent PCB traces. The co-simulation flow: extract the package model (the IC vendor provides an S-parameter or SPICE model of the package; for high-performance ICs: the vendor provides a 3D EM model or a detailed broadband IBIS-AMI model), extract the PCB model (simulate the PCB layout (traces, vias, planes, connectors) using a 3D EM solver (Ansys HFSS, Cadence EMX, Keysight EMPro) or a 2.5D solver (Ansys SIwave, Cadence PowerSI) to generate S-parameters or RLGC models), combine the models (connect the package model outputs to the PCB model inputs at the BGA pad interface), and run time-domain or frequency-domain analysis (simulate the complete signal path from the IC's die pad through the package through the BGA through the PCB trace to the far-end connector or receiver). Tools: Ansys HFSS + SIwave + Circuit: the most common commercial workflow for package-board co-simulation. Cadence Sigrity: provides integrated package and board analysis. Keysight ADS + EMPro: circuit-EM co-simulation.