What is the decoupling capacitor placement strategy for a BGA package on a high speed PCB?

The decoupling capacitor placement strategy for a BGA (Ball Grid Array) package on a high-speed PCB optimizes the location and value of ceramic capacitors to minimize the PDN impedance at the IC's power pins across all frequencies. The strategy follows a tiered approach: first priority: capacitors under the BGA (on the bottom side of the PCB, directly beneath the IC's power/ground balls; these capacitors have the shortest current loop (via down through the PCB, through the capacitor, and via back up), minimizing the loop inductance; the mounting inductance of a capacitor placed directly under the BGA is approximately 0.3-0.5 nH (vs. 1-3 nH for a capacitor placed next to the BGA); this low inductance makes these capacitors effective at higher frequencies (200 MHz-1 GHz). Capacitor size: 0201 or 0402 (the smallest sizes fit in the tight spacing between BGA vias). Values: 10 nF-100 nF (these are the most effective at 100 MHz-1 GHz due to their low ESL)), second priority: capacitors adjacent to the BGA (on the same side of the PCB, within 5-10 mm of the BGA perimeter; mounting inductance: 0.5-1.5 nH; effective at 50-500 MHz. Values: 100 nF-4.7 uF), and third priority: bulk capacitors nearby (within 10-25 mm; mounting inductance: 1-3 nH; effective at 1-100 MHz. Values: 4.7 uF-100 uF). Key principle: the effective bandwidth of a decoupling capacitor is determined by its mounting inductance more than its capacitance value. Minimizing the current loop area (close placement, short traces, direct via connections) is more important than adding more capacitance.