Software Defined Radio SDR Architecture Informational

What is the digital down converter in an SDR and how does it extract a narrowband signal from a wideband digitized spectrum?

The digital down converter (DDC) in an SDR is a digital signal processing function (typically implemented in an FPGA) that extracts a narrowband signal of interest from the wideband digitized spectrum captured by the ADC. The DDC performs three essential operations: frequency translation (mixing the digital samples with a numerically controlled oscillator, NCO, to shift the desired signal from its RF or IF frequency to baseband or near-DC), lowpass filtering (applying a digital filter to reject all signals outside the desired channel bandwidth), and decimation (reducing the sample rate to match the narrowband signal's Nyquist requirement, reducing the data rate that must be transferred and processed by the host). For example, an ADC sampling at 200 MSa/s digitizes a 100 MHz wide spectrum. A DDC tuned to extract a 25 kHz wide AM signal at 50 MHz IF would: multiply by a 50 MHz NCO (shifting the signal to 0 Hz), apply a digital lowpass filter with 25 kHz passband, and decimate by 4000 (reducing the output rate from 200 MSa/s to 50 kSa/s). The output is a complex (I/Q) baseband signal containing only the desired 25 kHz channel, at a data rate 4,000 times lower than the ADC output. This massive data rate reduction is what makes it practical to stream the selected channel to a host processor over standard interfaces.
Category: Software Defined Radio
Updated: April 2026
Product Tie-In: SDR Platforms, ADCs, FPGAs

Digital Down Conversion in Software Defined Radio

The DDC is the workhorse of SDR receive signal processing, performing the equivalent of analog tuning, filtering, and amplification entirely in the digital domain. Its ability to precisely tune to any frequency within the ADC bandwidth and extract channels of any width makes SDR fundamentally flexible.

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Common Questions

Frequently Asked Questions

Can I tune the DDC to any frequency within the ADC bandwidth?

Yes. The NCO has effectively infinite frequency resolution (limited only by the phase accumulator width, typically 32-48 bits); a 32-bit accumulator at 200 MHz sample rate provides 0.047 Hz resolution. The DDC can be tuned to any frequency from DC to f_s/2 with sub-hertz precision and phase-continuous frequency changes.

How many DDC channels can an FPGA support simultaneously?

It depends on the FPGA size, channel bandwidth, and filter complexity. A mid-range FPGA (Xilinx Kintex-7 325T) can support 8-16 independent DDC channels at 200 MSa/s with moderate filter complexity. A high-end FPGA (Virtex UltraScale+) can support 64-256+ channels. A polyphrase filter bank architecture is more efficient for large numbers of uniformly spaced channels.

What is the difference between DDC and a polyphase filter bank (PFB)?

A DDC extracts a single channel at an arbitrary frequency and bandwidth. It is flexible but requires one DDC instance per channel. A PFB divides the entire spectrum into uniformly spaced channels of equal bandwidth in a single operation using FFT, which is computationally more efficient for many channels but less flexible (fixed channel spacing and bandwidth). For receiving a few wideband channels at arbitrary frequencies, use DDCs. For channelizing the entire spectrum into many narrow channels, use a PFB.

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