What is the role of the FPGA in a software defined radio and what processing is typically done there?
FPGA Processing in Software Defined Radio Systems
The FPGA is often called the "digital front end" of the SDR. It performs the functions that are too fast for software but too flexible for fixed-function ASICs. Modern SDR FPGAs range from small devices (Xilinx Artix-7, Intel Cyclone V) in low-cost platforms to large devices (Xilinx Kintex UltraScale+, Intel Stratix 10) in high-performance systems.
Frequently Asked Questions
Can I use an SDR without an FPGA?
Yes, for low-bandwidth applications. Low-cost SDR dongles (RTL-SDR) use a fixed-function ASIC instead of an FPGA, which limits flexibility but reduces cost. For narrow bandwidth signals (< 2 MHz), the raw ADC data can be streamed directly to the host CPU for software processing. GNU Radio and similar frameworks can perform DDC and demodulation in software for data rates up to a few MSa/s on a modern laptop.
What FPGA size is needed for a typical SDR?
A basic single-channel SDR (one DDC, modest filter size) fits in a small FPGA with 50K logic cells and 100 DSP slices (Xilinx Artix-7 35T or similar). A multi-channel receiver with FFT and channelizer requires a mid-range FPGA (200K+ logic cells, 700+ DSP slices, Kintex-7 or Kintex UltraScale). Military/SIGINT systems with many channels and complex processing use high-end FPGAs (Virtex UltraScale+ or Stratix 10) with 5000+ DSP slices.
Is FPGA programming difficult for SDR?
FPGA development for SDR is significantly more complex than software development. VHDL/Verilog RTL design requires hardware engineering expertise. However, the SDR ecosystem has made this more accessible through: vendor-provided IP cores (DDC, DUC, FFT from Xilinx/AMD and Intel), open-source FPGA firmware (OpenCPI, USRP FPGA code), high-level synthesis tools (Vivado HLS, Intel HLS) that compile C/C++ to FPGA, and MATLAB/Simulink HDL Coder that generates FPGA code from signal processing models.