Analog-to-Digital Converter

ADC

/ay-dee-see/
An Analog-to-Digital Converter (ADC) converts a continuous analog RF or IF signal into discrete digital samples for processing by DSP, FPGA, or software. ADC performance is characterized by sampling rate (GSPS), resolution (bits), SNR, SFDR (spurious-free dynamic range), and effective number of bits (ENOB). Modern high-speed ADCs enable direct RF sampling at frequencies up to 10+ GHz.
Category: Data Conversion
Related to: DAC, Sampling, Bandwidth, SNR, SFDR
Units: GSPS, bits, dBFS

Understanding ADCs in RF

ADCs are the gateway between the analog RF world and digital signal processing. They determine the maximum instantaneous bandwidth, dynamic range, and sensitivity of a digital receiver. The push toward software-defined radio (SDR) and direct RF sampling has made ADC technology a critical enabler of modern RF systems.

Key Specifications

  • Sampling rate: Maximum sample clock speed. Determines maximum input bandwidth (Nyquist: BW = fs/2).
  • Resolution: Number of bits per sample. Each bit adds ~6 dB of dynamic range.
  • ENOB: Effective number of bits at a given input frequency. Always less than nominal resolution.
  • SFDR: Difference between signal and largest spurious product. Determines receiver sensitivity in the presence of large signals.

RF Sampling Architectures

  • Baseband sampling: ADC samples after downconversion to baseband. Moderate speed. Standard approach.
  • IF sampling: ADC samples at IF (hundreds of MHz). Uses undersampling or Nyquist sampling.
  • Direct RF sampling: ADC samples the RF signal directly. Eliminates mixer and LO. Requires very high-speed ADCs (10+ GSPS).
Common Questions

Frequently Asked Questions

What does an ADC do in RF?

An ADC converts the analog received signal into digital samples that can be processed by DSP software. It determines the maximum bandwidth, dynamic range, and precision of the digital receiver. Higher-speed, higher-resolution ADCs enable more capable receivers.

What is direct RF sampling?

Direct RF sampling uses a very high-speed ADC to digitize signals directly at the RF frequency without a mixer or IF stage. This simplifies the receiver architecture and enables software-defined flexibility. It requires ADCs sampling at 10+ GSPS with good SFDR.

What limits ADC performance at RF?

At higher input frequencies, ADC jitter and aperture uncertainty degrade ENOB and SFDR. Clock jitter of 100fs limits SNR to about 60 dB at 5 GHz input even with a 14-bit ADC. Thermal noise and comparator metastability also degrade performance.

Digital Receiver Solutions

Talk to Our Engineers

For ADC selection and digital receiver design, contact our team.

Get in Touch