Signal Integrity and High Speed Digital Additional SI Topics Informational

How does the ISI penalty in a lossy channel affect the eye opening at the receiver?

The ISI (Inter-Symbol Interference) penalty in a lossy channel affects the eye opening at the receiver by reducing both the vertical (voltage) and horizontal (timing) eye margins, making it harder for the receiver to correctly distinguish between a logic 1 and logic 0. The mechanism: a lossy channel (PCB traces, connectors, cables) attenuates higher-frequency signal components more than lower-frequency ones (the loss increases approximately as sqrt(f) for skin-effect dominated channels). This frequency-dependent attenuation distorts the signal: a sharp transition (which has high-frequency content) is rounded and elongated. The tail of one bit's response extends into subsequent bit periods, interfering with their detection (this is the inter-symbol interference). The ISI penalty: the eye voltage opening shrinks because the residual energy from previous bits adds constructively or destructively, depending on the data pattern (a long run of 1s followed by a 0 has a different voltage than an alternating 0-1-0 pattern). The worst-case eye voltage at the receiver: V_eye = V_cursor - sum(|V_postcursor_i| + |V_precursor_j|), where V_cursor is the main cursor amplitude (the desired bit's voltage), and V_postcursor/precursor are the residual voltages from adjacent bits. For a 28 Gbps NRZ signal on a 20-inch FR-4 trace (approximately 25 dB loss at Nyquist): the unequalized eye is essentially closed (ISI exceeds the signal amplitude). After equalization (CTLE + 5-tap DFE): the eye opens to approximately 40-60% of the original amplitude.
Category: Signal Integrity and High Speed Digital
Updated: April 2026
Product Tie-In: PCB Materials, Test Equipment

ISI and Eye Opening

ISI is the dominant signal integrity challenge for high-speed serial links. Understanding ISI is essential for: channel design (choosing PCB materials, trace lengths, and connectors), equalization design (sizing the CTLE and DFE to compensate for the channel), and jitter budgeting (ISI is the largest deterministic jitter contributor).

  • Performance verification: confirm specifications against the application requirements before finalizing the design
  • Environmental factors: temperature range, humidity, and vibration affect long-term reliability and parameter drift
  • Cost vs. performance: evaluate whether the application demands premium components or standard commercial grades
  • Interface compatibility: verify impedance, connector type, and mechanical form factor match the system architecture
  • Margin allocation: include sufficient design margin to account for manufacturing tolerances and aging effects
Common Questions

Frequently Asked Questions

How much loss can equalization handle?

Modern equalizers can recover signals from channels with 30-50+ dB of loss at the Nyquist frequency: CTLE (Continuous-Time Linear Equalizer): compensates for 10-20 dB of loss by boosting high frequencies. Limited by noise enhancement (boosting also amplifies noise). DFE (Decision Feedback Equalizer): cancels 10-20 dB of post-cursor ISI by subtracting the estimated ISI from each received bit. Does not enhance noise. FFE (Feed-Forward Equalizer) at the transmitter: applies pre-emphasis to boost high-frequency components before transmission. Compensates for 5-15 dB. Combined: CTLE + DFE + TX FFE can recover eyes from channels with 40-60 dB of loss. Example: 112G PAM4 links operate with 30-40 dB of channel loss using advanced equalization.

What about PAM4?

PAM4 (4-level Pulse Amplitude Modulation): uses four voltage levels instead of two (NRZ). This doubles the data rate per symbol but: reduces the eye height by 3× (the four levels are spaced at V/3 instead of V). The ISI penalty is much more severe for PAM4 because: the smaller eye height means less margin for ISI-induced voltage error, and the four-level signaling creates more complex ISI patterns. Result: PAM4 channels require: lower-loss PCB materials (Megtron 6, Tachyon-100G: 0.3-0.5 dB/inch at 14 GHz vs. 1.5-2.5 dB/inch for FR-4), and more powerful equalization (more DFE taps, better CTLE, and CDR with advanced phase tracking).

How do I simulate ISI?

Channel simulation tools: Keysight ADS Channel Simulation: the industry standard for SerDes channel analysis. Uses S-parameters of the channel (from EM simulation or VNA measurement) and IBIS-AMI models of the TX/RX to simulate the eye diagram, BER, and jitter. Ansys Designer: similar channel simulation capability with integration to HFSS for EM extraction. Cadence Sigrity SystemSI: board-level channel simulation. Free/open-source: PyBERT (Python-based BER tool): simulates NRZ and PAM4 channels with equalization. Uses S-parameters and analytical TX/RX models. Excellent for educational and preliminary analysis.

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