How do I select the ADC for an SDR to achieve the required spurious free dynamic range?
ADC Selection for SDR Spurious-Free Dynamic Range
The ADC is arguably the most critical component in an SDR receiver. Its performance ceiling defines the maximum achievable sensitivity, dynamic range, and signal fidelity of the entire system. No amount of subsequent digital processing can recover information lost at the ADC.
- Performance verification: confirm specifications against the application requirements before finalizing the design
- Environmental factors: temperature range, humidity, and vibration affect long-term reliability and parameter drift
- Cost vs. performance: evaluate whether the application demands premium components or standard commercial grades
Frequently Asked Questions
Is a 16-bit ADC always better than a 14-bit for SDR?
Not always. At high input frequencies and high sample rates, the additional 2 bits of theoretical resolution may not translate to real improvement because the ENOB of both 14-bit and 16-bit ADCs converges due to jitter and analog imperfections. A 16-bit ADC at 500 MSa/s may have ENOB of only 11-12 bits at 500 MHz input, not much better than a well-designed 14-bit ADC. The 16-bit advantage is most significant at lower input frequencies where quantization noise dominates.
How important is the clock source for ADC performance?
Extremely important. Clock jitter is often the performance-limiting factor for high-frequency inputs. At 1 GHz input frequency, 100 fs RMS jitter limits SNR to 64 dB regardless of ADC bit count. At 100 MHz input, 100 fs limits SNR to 84 dB. Use low-jitter clock sources (VCXO or SAW oscillator with integrated jitter < 50 fs) and minimize jitter added by the clock distribution network.
What is the dithering technique for ADC SFDR improvement?
Adding controlled noise (dither) to the ADC input randomizes the quantization error, converting harmonic spurs into broadband noise. This improves SFDR at the expense of slightly higher noise floor. Dithering is useful when the signal of interest may have a frequency that creates coherent quantization spurs. It is implemented by injecting a small analog noise signal or by adding digital noise at the ADC input.