How do I perform harmonic balance simulation of a power amplifier using a transistor model?
HB Simulation for PA Design
Harmonic balance is the foundation of modern PA design simulation. It is far more efficient than time-domain (transient) simulation for steady-state periodic circuits because it directly solves for the frequency-domain solution.
| Parameter | Option A | Option B | Option C |
|---|---|---|---|
| Performance | High | Medium | Low |
| Cost | High | Low | Medium |
| Complexity | High | Low | Medium |
| Bandwidth | Narrow | Wide | Moderate |
| Typical Use | Lab/military | Consumer | Industrial |
Technical Considerations
(1) Number of harmonics: for PA simulation: use at least N = 7 harmonics (f0 through 7f0). Fewer harmonics can miss the clipping behavior at high drive levels. For mixer simulation: include both the RF and LO frequencies and their intermodulation products. For intermodulation (two-tone) simulation: use a separate analysis type (multi-tone HB or envelope simulation). (2) Power sweep: to characterize the PA gain compression, simulate across a range of input power levels (e.g., P_in = -20 to +20 dBm in 1 dB steps). The power sweep produces: gain vs P_in (showing the 1 dB compression point), P_out vs P_in (showing the saturated output power), PAE vs P_in (showing the peak efficiency), and harmonic output vs P_in (showing the spectral regrowth). (3) Load impedance: the PA performance depends on the load impedance. For initial design: set the load to 50 ohms and observe the baseline performance. For optimization: perform load-pull simulation (sweep the load impedance across the Smith chart and plot contours of P_out and PAE). The optimal load impedance (Gamma_opt) provides the maximum P_out or maximum PAE. Design the output matching network to present Gamma_opt to the transistor. (4) Bias: set the gate and drain bias voltages according to the target operating class: Class A: V_GS at 50% of I_DSS. Highest linearity, lowest efficiency (PAE ≈ 25-40%). Class AB: V_GS at 10-20% of I_DSS. Good linearity-efficiency tradeoff (PAE ≈ 40-60%). Class B: V_GS at pinch-off (I_DS ≈ 0 at quiescent). Higher efficiency (PAE ≈ 50-70%) but more distortion. Monitor: the DC current (I_DS_Q) should match the expected quiescent current for the chosen class.
- Performance verification: confirm specifications against the application requirements before finalizing the design
- Environmental factors: temperature range, humidity, and vibration affect long-term reliability and parameter drift
- Cost vs. performance: evaluate whether the application demands premium components or standard commercial grades
Performance Analysis
(1) Non-convergence: the Newton-Raphson solver fails to find a solution. Common causes: the transistor model has a discontinuity (a kink in the I-V curves). The matching network has a very high-Q resonance (the solution changes rapidly with frequency). The circuit is oscillating (an unstable PA with feedback that causes oscillation). Fix: increase the number of harmonics. Add damping (a small resistor in series with a reactive element). Verify the model does not have kinks (plot the I-V curves and check for smoothness). Check for oscillation (the K-factor or stability circles should show unconditional stability within the design bandwidth). (2) Slow convergence: the simulation takes many iterations. Cause: the circuit is highly nonlinear (deep compression, switching-mode PA). Fix: use a good initial guess (start with a lower input power and use the converged solution as the initial guess for the next power level). Use the "power sweep" analysis type (which automatically uses the previous solution as the starting point). (3) Multi-tone convergence: two-tone HB simulation is harder to converge because the intermodulation products create a dense frequency spectrum. Use envelope simulation instead (it represents the modulation as a time-varying envelope around the carrier, reducing the number of frequency components).
Frequently Asked Questions
How is HB different from transient simulation?
Transient simulation (SPICE-like): solves the circuit equations in the time domain step by step. Must simulate until the circuit reaches steady state (may take thousands of RF cycles). Very slow for high-Q circuits (the Q cycles must all be simulated). Accurate for non-periodic and startup behavior. Used for: digital circuits, oscillator startup, and circuits with non-periodic excitation. Harmonic balance: directly solves for the steady-state periodic solution in the frequency domain. Does not need to simulate the startup transient (jumps directly to the final answer). Very fast for periodic circuits (PA, mixer, frequency multiplier). Cannot simulate non-periodic behavior (startup, transient response). Used for: PA compression curves, mixer conversion loss, frequency multiplier efficiency, and any periodic steady-state analysis. For PA design: HB is 100-1000× faster than transient simulation and provides the same steady-state result.
What about modulated signals (5G OFDM)?
A 5G OFDM signal is not periodic (it is a superposition of many subcarriers with random data). Standard HB cannot directly simulate non-periodic signals. Solutions: (1) Envelope simulation: the input signal is decomposed into a slowly varying envelope modulating a carrier. The HB solver handles the carrier (periodic), and a time-domain solver handles the envelope (slowly varying). This is the standard method for PA simulation with modulated signals. (2) Two-tone simulation: approximate the modulated signal with two CW tones separated by the modulation bandwidth. The IM3 (third-order intermodulation) from the two-tone simulation predicts the ACLR (adjacent channel leakage ratio) of the modulated signal. This is a quick approximation (the exact ACLR depends on the signal statistics). (3) Circuit envelope (CE) simulation: a hybrid solver available in Keysight ADS and Cadence AWR. It combines HB (for the carrier) with a transient solver (for the envelope). The envelope is sampled at the modulation rate (e.g., 100 MHz for a 5G signal). Each sample is a separate HB solution. This provides: EVM, ACLR, and spectral regrowth for the actual 5G signal. CE simulation is 10-100× slower than single-tone HB but provides the most accurate result for modulated signals.
How do I use load-pull in HB simulation?
Load-pull simulation systematically varies the load impedance and evaluates the PA performance at each impedance: (1) Setup: define a load tuner that sweeps Gamma_L across the Smith chart (typically 100-500 load impedance points). At each Gamma_L: run an HB simulation and record P_out, PAE, gain, and harmonics. (2) Plot: contours of constant P_out (e.g., -1 dB, -2 dB, -3 dB from the maximum P_out) on the Smith chart. The contour shapes show how sensitive the PA is to load impedance mismatch. Similarly: contours of constant PAE. The PAE-optimal load may differ from the P_out-optimal load by 5-15° on the Smith chart. (3) Design decision: choose the load impedance that provides the best compromise between P_out and PAE (often 0.5-1 dB below maximum P_out but at 3-5% higher PAE). Design the output matching network to present this load to the transistor at f0 and to present a conjugate match at the harmonics (for specific PA classes: class F requires a short at 2f0 and an open at 3f0).