Semiconductor and Device Technology Device Physics and Modeling Informational

How do I extract a nonlinear transistor model from measured S-parameters and DC IV curves?

A nonlinear transistor model is constructed by combining DC I-V (current-voltage) measurements with multi-bias S-parameter measurements to capture both the static and dynamic behavior of the device: (1) DC I-V measurement: measure the drain current (I_DS) as a function of gate voltage (V_GS) and drain voltage (V_DS). This provides: the transconductance (g_m = dI_DS/dV_GS), the output conductance (g_ds = dI_DS/dV_DS), the threshold voltage (V_th), the knee voltage (V_knee), and the maximum current (I_DSS). These parameters define the nonlinear current source in the model (the core of the transistor model). (2) Multi-bias S-parameter measurement: measure the small-signal S-parameters at multiple bias points (varying V_GS and V_DS across the operating range). At each bias point: the S-parameters capture the linear behavior (gain, input/output impedance, feedback). From the S-parameters: extract the small-signal equivalent circuit elements at each bias: intrinsic elements (C_gs, C_gd, C_ds, g_m, g_ds, R_i, tau) and extrinsic elements (L_g, L_d, L_s, R_g, R_d, R_s, C_pg, C_pd). The extrinsic elements are bias-independent (they represent the physical parasitics of the device: pad capacitances, lead inductances, contact resistances). The intrinsic elements are bias-dependent (they represent the active device behavior). (3) Model construction: choose a model topology: Angelov (for GaN and GaAs HEMTs), Curtice (for GaAs FETs), or VBIC/HiCUM (for HBTs). Fit the nonlinear current source equations to the DC I-V data. Map the bias-dependent intrinsic elements (C_gs(V_GS, V_DS), C_gd(V_GS, V_DS), etc.) to the model charge equations. Fit the model parameters to reproduce the measured S-parameters across all bias points. (4) Verification: simulate the device with the extracted model and compare to: measured S-parameters at bias points NOT used in the extraction (interpolation test), measured large-signal data (load-pull, power sweep) if available, and harmonic behavior (second and third harmonic output vs input power).
Category: Semiconductor and Device Technology
Updated: April 2026
Product Tie-In: Transistors, Simulation Tools

Nonlinear Model Extraction

Nonlinear model extraction is a critical skill in MMIC design. The model quality directly determines whether the simulated PA/LNA/mixer performance matches the fabricated hardware.

  • Performance verification: confirm specifications against the application requirements before finalizing the design
  • Environmental factors: temperature range, humidity, and vibration affect long-term reliability and parameter drift
  • Cost vs. performance: evaluate whether the application demands premium components or standard commercial grades
  • Interface compatibility: verify impedance, connector type, and mechanical form factor match the system architecture
  • Margin allocation: include sufficient design margin to account for manufacturing tolerances and aging effects
Common Questions

Frequently Asked Questions

How many bias points do I need for extraction?

Minimum: a 5×5 grid (5 V_GS values × 5 V_DS values = 25 bias points). This covers: V_GS from below V_th to above the max operating V_GS. V_DS from 0 to the maximum operating V_DS. Recommended: 7×7 to 10×10 grid (49-100 bias points). More points = better capture of the nonlinear behavior at the transitions (near pinch-off, near saturation). For each bias point: measure S-parameters from 0.1 GHz to at least 2× the operating frequency (e.g., 0.1-67 GHz for a 28 GHz PA). The frequency range must exceed the operating frequency to capture the frequency dependence of the intrinsic elements.

What if I do not have access to on-wafer measurements?

If the device is packaged (not bare die): (1) Measure the packaged device S-parameters on a test fixture (PCB with connectorized access). (2) De-embed the fixture (using TRL calibration or a known fixture model). (3) The de-embedded S-parameters include both the device and the package parasitics. (4) Extract the package model first (from measurements of an empty package or from the package datasheet). (5) De-embed the package to obtain the die-level S-parameters. (6) Proceed with the standard extraction flow. Alternatively: if the device manufacturer provides a nonlinear model: use it directly. Verify by comparing the model S-parameters with your measured packaged-device S-parameters (including the package model). If they agree within 1-2 dB: the model is trustworthy.

How do I verify the model before taping out a MMIC?

Verification steps: (1) S-parameter comparison: overlay the model S-parameters with the measured S-parameters at 5-10 bias points NOT used in the extraction. The agreement should be within: |S11|: ±1 dB, |S21|: ±0.5 dB, |S22|: ±1 dB, phase of S21: ±5°, for all frequencies up to 2× the operating frequency. (2) Large-signal verification: if load-pull data is available: compare the model load-pull contours (P_out, PAE, gain vs load impedance) with measured load-pull. The optimal load impedance should agree within ±2° on the Smith chart. P_out and PAE should agree within ±0.5 dB and ±3%, respectively. (3) Harmonic verification: measure the second and third harmonic output power vs input power. The model should predict the harmonic levels within ±3 dB. If the large-signal verification fails: the model may have issues with the nonlinear current source or charge model. Refit those parameters using the large-signal data as additional optimization targets.

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