How do I extract a nonlinear transistor model from measured S-parameters and DC IV curves?
Nonlinear Model Extraction
Nonlinear model extraction is a critical skill in MMIC design. The model quality directly determines whether the simulated PA/LNA/mixer performance matches the fabricated hardware.
| Parameter | Option A | Option B | Option C |
|---|---|---|---|
| Performance | High | Medium | Low |
| Cost | High | Low | Medium |
| Complexity | High | Low | Medium |
| Bandwidth | Narrow | Wide | Moderate |
| Typical Use | Lab/military | Consumer | Industrial |
Technical Considerations
(1) Step 1: de-embed the pad parasitics. The on-wafer measurements include the probe pads and access lines. These must be removed (de-embedded) to obtain the device-only characteristics. De-embedding structures: open, short, and thru standards fabricated on the same wafer as the device. Two-step de-embedding: subtract the open parasitic capacitance, then subtract the short parasitic inductance. (2) Step 2: extract the extrinsic elements. At a bias where the device is fully pinched off (V_GS << V_th, all channels depleted): the intrinsic device looks like a simple capacitor network. The extrinsic elements dominate the measured S-parameters. Extract R_g, R_d, R_s, L_g, L_d, L_s from the pinch-off S-parameters. Cold-FET technique: bias at V_DS = 0 and forward-bias the gate (V_GS > 0). Under forward bias: the channel is a resistor (the intrinsic elements are known). The extrinsic elements are extracted from the difference between measured and known intrinsic. (3) Step 3: extract the intrinsic elements at each bias. Subtract the extrinsic network from the measured S-parameters. Convert the de-embedded S-parameters to Y-parameters. Extract: g_m = Re(Y21), C_gs = Im(Y11-Y12)/omega, C_gd = -Im(Y12)/omega, C_ds = Im(Y22+Y12)/omega, g_ds = Re(Y22), R_i = Re(1/(Y11+Y12)), and tau = delay time from the phase of Y21. (4) Step 4: fit the nonlinear model. The model uses equations (Angelov, Curtice, or other) that parametrize the bias dependence of each element. Fit the equation coefficients to the extracted element values across all bias points. Optimization: use a least-squares optimizer to find the coefficients that minimize the error between the model S-parameters and the measured S-parameters across all frequencies and bias points simultaneously.
Performance Analysis
(1) Angelov (also called Chalmers model): the most widely used model for GaN and GaAs HEMTs in PA design. The drain current is modeled as: I_DS = I_PK × (1 + tanh(psi)) × tanh(alpha × V_DS). Where psi is a polynomial in V_GS. The parameters (I_PK, psi coefficients, alpha) are fitted to the DC I-V data. The charge model (for C_gs, C_gd, C_ds) uses a charge-conservative formulation that ensures physical consistency. (2) Curtice: an older model for GaAs MESFETs and early pHEMTs. Simpler equations (cubic or quadratic drain current). Still used for quick modeling of simple devices. (3) EE-HEMT (Keysight): an empirical model with a large number of fitting parameters. Very flexible (can fit almost any I-V shape). Risk: overfitting (the model fits the measured data perfectly but predicts poorly at unmeasured conditions). (4) Physics-based models (TCAD): derived from semiconductor physics (drift-diffusion or Monte Carlo simulation). Very accurate but computationally expensive. Used for: device design and process development (not typically for circuit design).
Design Guidelines
When evaluating extract a nonlinear transistor model from measured s-parameters and dc iv curves?, engineers must account for the specific requirements of their target application. The optimal choice depends on the frequency range, power level, environmental conditions, and cost constraints of the overall system design.
- Performance verification: confirm specifications against the application requirements before finalizing the design
- Environmental factors: temperature range, humidity, and vibration affect long-term reliability and parameter drift
- Cost vs. performance: evaluate whether the application demands premium components or standard commercial grades
- Interface compatibility: verify impedance, connector type, and mechanical form factor match the system architecture
- Margin allocation: include sufficient design margin to account for manufacturing tolerances and aging effects
Implementation Notes
When evaluating extract a nonlinear transistor model from measured s-parameters and dc iv curves?, engineers must account for the specific requirements of their target application. The optimal choice depends on the frequency range, power level, environmental conditions, and cost constraints of the overall system design.
Frequently Asked Questions
How many bias points do I need for extraction?
Minimum: a 5×5 grid (5 V_GS values × 5 V_DS values = 25 bias points). This covers: V_GS from below V_th to above the max operating V_GS. V_DS from 0 to the maximum operating V_DS. Recommended: 7×7 to 10×10 grid (49-100 bias points). More points = better capture of the nonlinear behavior at the transitions (near pinch-off, near saturation). For each bias point: measure S-parameters from 0.1 GHz to at least 2× the operating frequency (e.g., 0.1-67 GHz for a 28 GHz PA). The frequency range must exceed the operating frequency to capture the frequency dependence of the intrinsic elements.
What if I do not have access to on-wafer measurements?
If the device is packaged (not bare die): (1) Measure the packaged device S-parameters on a test fixture (PCB with connectorized access). (2) De-embed the fixture (using TRL calibration or a known fixture model). (3) The de-embedded S-parameters include both the device and the package parasitics. (4) Extract the package model first (from measurements of an empty package or from the package datasheet). (5) De-embed the package to obtain the die-level S-parameters. (6) Proceed with the standard extraction flow. Alternatively: if the device manufacturer provides a nonlinear model: use it directly. Verify by comparing the model S-parameters with your measured packaged-device S-parameters (including the package model). If they agree within 1-2 dB: the model is trustworthy.
How do I verify the model before taping out a MMIC?
Verification steps: (1) S-parameter comparison: overlay the model S-parameters with the measured S-parameters at 5-10 bias points NOT used in the extraction. The agreement should be within: |S11|: ±1 dB, |S21|: ±0.5 dB, |S22|: ±1 dB, phase of S21: ±5°, for all frequencies up to 2× the operating frequency. (2) Large-signal verification: if load-pull data is available: compare the model load-pull contours (P_out, PAE, gain vs load impedance) with measured load-pull. The optimal load impedance should agree within ±2° on the Smith chart. P_out and PAE should agree within ±0.5 dB and ±3%, respectively. (3) Harmonic verification: measure the second and third harmonic output power vs input power. The model should predict the harmonic levels within ±3 dB. If the large-signal verification fails: the model may have issues with the nonlinear current source or charge model. Refit those parameters using the large-signal data as additional optimization targets.