What is the role of an FPGA in a software defined radio architecture?
FPGA in SDR
The Zynq UltraScale+ RFSoC integrates up to 16 ADCs (14-bit, 5 GSPS) and 16 DACs (14-bit, 10 GSPS) on the same die as the FPGA fabric and ARM processors. This eliminates the high-speed data interface between discrete ADCs and the FPGA, reducing power, board area, and design complexity. RFSoC has become the standard platform for 5G base stations, military SDR, and wideband SIGINT receivers.
| Parameter | Pipeline ADC | SAR ADC | Sigma-Delta ADC |
|---|---|---|---|
| Sample Rate | 100 MS/s - 10 GS/s | 1-100 MS/s | 10 kS/s - 50 MS/s |
| Resolution | 8-14 bits | 10-20 bits | 16-24 bits |
| Latency | Several clock cycles | 1 conversion cycle | Many cycles (decimation) |
| Power | High | Low-moderate | Low |
| Typical RF Use | Direct sampling, DPD | Control, monitoring | Audio, baseband |
- Performance verification: confirm specifications against the application requirements before finalizing the design
- Environmental factors: temperature range, humidity, and vibration affect long-term reliability and parameter drift
- Cost vs. performance: evaluate whether the application demands premium components or standard commercial grades
Frequently Asked Questions
FPGA vs GPU for SDR?
FPGA: lower latency (deterministic ns timing), lower power for sustained streaming processing, and direct ADC/DAC interface. Best for real-time, continuous processing chains (DDC, channelization, beamforming). GPU: higher peak throughput for parallelizable algorithms, easier programming (CUDA/OpenCL), but higher latency and power. Best for burst processing (spectral analysis, machine learning inference).
How do I size the FPGA?
Key resources: DSP slices (each implements one complex multiply-add, needed for filtering and beamforming), block RAM (stores filter coefficients, FFT twiddle factors, and data buffers), and logic cells (control, routing, interfaces). A single DDC channel at 1 GSPS needs approximately 50-100 DSP slices. A 256-point FFT: approximately 200 DSP slices. Start with the processing chain requirements and multiply by the number of parallel channels.