Digital and Mixed Signal RF Digital Signal Processing for RF Informational

How do I design a digital IF filter for a software defined radio receiver?

Q: What filter specifications are needed for 5G NR?

For 5G NR FR1 (sub-6 GHz): channel bandwidths from 5 to 100 MHz. The channel filter must pass the full OFDM signal bandwidth with 50 dB adjacent channel rejection (to meet ACLR requirements), and have linear phase across the passband (group delay ripple < 10 ns peak-to-peak). For 100 MHz channel bandwidth at 200 MSa/s: a 64-tap FIR with 25 MHz transition band achieves 60 dB rejection. For 5 MHz bandwidth at 200 MSa/s: a 500+ tap FIR or multi-stage decimation chain is needed.

Q: Can I use an IIR filter for channel selection?

IIR filters can be used if the phase distortion is acceptable. For constant-modulus signals (FM, FSK, PSK with differential encoding): IIR phase distortion causes no performance degradation. For amplitude-sensitive modulations (QAM, OFDM): IIR group delay variation degrades EVM. Mitigation: use an all-pass phase equalizer after the IIR to flatten the group delay (adds complexity). Alternative: use an IIR for coarse channel selection (wide bandwidth, low order) followed by an FIR for fine equalization and final filtering. This hybrid approach reduces total computation while maintaining signal quality.

Designing a digital IF filter for a software defined radio (SDR) receiver requires selecting the filter architecture (FIR or IIR), determining the filter order from the selectivity requirements, and implementing the filter efficiently on an FPGA or DSP. The IF digitization approach: an ADC samples the IF signal (typically 10-200 MHz) at a rate satisfying Nyquist (f_sample > 2 × f_IF_max). The digital IF filter then selects the desired channel from the digitized spectrum. FIR filters are preferred for SDR due to linear phase response (no group delay distortion), guaranteed stability, and straightforward FPGA implementation using multiply-accumulate (MAC) operations. Design procedure: (1) Specify passband bandwidth (equal to the channel bandwidth, e.g., 200 kHz for GSM, 20 MHz for LTE), transition bandwidth (determines filter order: narrower transition requires higher order), passband ripple (<0.1 dB for minimal signal distortion), and stopband rejection (>60 dB for adequate adjacent-channel rejection). (2) Calculate filter order using the Parks-McClellan (equiripple) or Kaiser window method: N ≈ -20×log10(sqrt(delta_p × delta_s)) - 13) / (14.6 × delta_f / f_sample), where delta_p is passband ripple, delta_s is stopband attenuation (linear), and delta_f is transition bandwidth. For a 200 kHz channel with 50 kHz transition band, 0.01 dB ripple, 80 dB rejection at 100 MSa/s: N ≈ 400 taps. (3) Implement using polyphase decomposition for efficient downsampling: decompose the N-tap filter into M polyphase branches (M = decimation factor), reducing the computation rate by M. For M = 500 (decimating from 100 MSa/s to 200 kSa/s): each polyphase branch has only 1 tap, dramatically reducing processing requirements.

Category: Digital and Mixed Signal RF

Updated: April 2026

Product Tie-In: FPGAs, SDR Platforms, DSP Modules

SDR Digital IF Filter Design

Digital IF filtering is the core signal processing function in an SDR receiver, replacing analog crystal and ceramic filters with flexible, reconfigurable digital implementations that can adapt to any standard or waveform.

Parameter	Pipeline ADC	SAR ADC	Sigma-Delta ADC
Sample Rate	100 MS/s - 10 GS/s	1-100 MS/s	10 kS/s - 50 MS/s
Resolution	8-14 bits	10-20 bits	16-24 bits
Latency	Several clock cycles	1 conversion cycle	Many cycles (decimation)
Power	High	Low-moderate	Low
Typical RF Use	Direct sampling, DPD	Control, monitoring	Audio, baseband

Sampling and Quantization

FIR (Finite Impulse Response): advantages include exact linear phase (essential for preserving modulation quality), guaranteed stability (all poles at the origin), and easily mapped to FPGA fabric (regular multiply-accumulate structure). Disadvantage: high order required for narrow transition bands (400+ taps for narrow-channel applications), demanding many multipliers. IIR (Infinite Impulse Response): advantages include much lower order for equivalent selectivity (a 6th-order elliptic IIR matches a 200-tap FIR for the same specifications). Disadvantage: nonlinear phase (causes group delay distortion, degrading EVM for wideband modulations), potential stability issues with fixed-point arithmetic (coefficient quantization can move poles outside the unit circle), and less FPGA-friendly (feedback paths create timing challenges). Recommendation: use FIR for the channel selection filter (where phase linearity matters) and IIR for anti-aliasing and DC-removal preprocessing (where phase is less critical).

Dynamic Range Considerations

Modern FPGAs (Xilinx Zynq UltraScale+, Intel Agilex) contain dedicated DSP blocks (multiply-accumulate units) optimized for filter implementations. A single DSP block operates at 500-800 MHz and performs one 18×18 or 27×18 multiply-accumulate per clock cycle. For a 400-tap FIR filter running at 100 MSa/s: direct implementation requires 400 multiplications per sample × 100M samples/s = 40 GMAC/s. An FPGA with 2000 DSP blocks at 500 MHz provides 1000 GMAC/s, easily handling this workload. Optimization techniques: (1) Symmetric coefficient exploitation: for linear-phase FIR, coefficients are symmetric (h[n] = h[N-1-n]), halving the multiplier count. (2) Polyphase decomposition: for decimating filters, reduces computation by the decimation factor. (3) Multi-rate implementation: cascade a coarse decimating filter (low order, wide transition) with a fine channel filter (high order, narrow transition). Each stage operates at its own rate, minimizing total computation. (4) Coefficient quantization: use 16-18 bit coefficients for 80+ dB stopband rejection. 12-bit coefficients limit rejection to ~70 dB.

Performance verification: confirm specifications against the application requirements before finalizing the design
Environmental factors: temperature range, humidity, and vibration affect long-term reliability and parameter drift
Cost vs. performance: evaluate whether the application demands premium components or standard commercial grades
Interface compatibility: verify impedance, connector type, and mechanical form factor match the system architecture

Clock and Timing

A typical SDR receiver filter chain: (1) ADC anti-alias filter (analog): low-pass, sets the Nyquist bandwidth. (2) DDC (Digital Downconverter): NCO (numerically controlled oscillator) + mixer shifts the desired channel to baseband. Implemented as cos/sin multiplication using CORDIC or a lookup table. (3) CIC (Cascaded Integrator-Comb) filter: coarse decimation by factor 10-100. CIC requires no multipliers (only adders and delays), very efficient for high decimation ratios. Passband droop: correctable with a short FIR compensator. (4) Half-band filter: decimation by 2, exploiting the fact that every other coefficient is zero (halves the multiplier count). May cascade 2-3 half-band stages. (5) Channel filter (FIR): final channel selection with specified bandwidth, transition, and rejection. This multi-stage approach is far more efficient than a single filter: total computation for a 100 MSa/s to 200 kSa/s processing chain is typically 50-200 MMAC/s instead of 40 GMAC/s for a brute-force single-stage approach.

Common Questions

Frequently Asked Questions

How many FPGA resources does a typical SDR filter chain require?

For a wideband SDR (100 MSa/s ADC, 10 simultaneous channels): DDC: ~5 DSP blocks per channel (NCO + mixer). CIC: <1% of FPGA logic (no multipliers). Half-band filters: 15-30 DSP blocks per channel. Channel filter: 50-200 DSP blocks per channel. Total per channel: 70-235 DSP blocks. For 10 channels: 700-2350 DSP blocks. A mid-range FPGA (Xilinx ZU4EV: 728 DSP blocks) handles 3-10 channels. A high-end FPGA (Xilinx ZU28DR: 4272 DSP blocks) handles 18-60 channels. Memory (BRAM) for coefficient storage and delay lines: 1-5 Mb per channel. Total power: 5-15W for the FPGA portion of a 10-channel SDR receiver.

What filter specifications are needed for 5G NR?

For 5G NR FR1 (sub-6 GHz): channel bandwidths from 5 to 100 MHz. The channel filter must pass the full OFDM signal bandwidth with < 0.05 dB passband ripple (to maintain EVM < 1%), provide > 50 dB adjacent channel rejection (to meet ACLR requirements), and have linear phase across the passband (group delay ripple < 10 ns peak-to-peak). For 100 MHz channel bandwidth at 200 MSa/s: a 64-tap FIR with 25 MHz transition band achieves 60 dB rejection. For 5 MHz bandwidth at 200 MSa/s: a 500+ tap FIR or multi-stage decimation chain is needed.

Can I use an IIR filter for channel selection?

IIR filters can be used if the phase distortion is acceptable. For constant-modulus signals (FM, FSK, PSK with differential encoding): IIR phase distortion causes no performance degradation. For amplitude-sensitive modulations (QAM, OFDM): IIR group delay variation degrades EVM. Mitigation: use an all-pass phase equalizer after the IIR to flatten the group delay (adds complexity). Alternative: use an IIR for coarse channel selection (wide bandwidth, low order) followed by an FIR for fine equalization and final filtering. This hybrid approach reduces total computation while maintaining signal quality.

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