How does a PLL frequency synthesizer work?

A PLL synthesizer consists of a reference oscillator, phase/frequency detector (PFD), charge pump, loop filter, VCO, and feedback divider. The reference oscillator (typically a crystal at 10 to 100 MHz) is divided by R to produce the comparison frequency f_comp = f_ref/R. The VCO output is divided by N to produce f_VCO/N. The PFD compares these two frequencies and generates an error signal proportional to their phase difference. The charge pump converts this to a current pulse, and the loop filter integrates it to produce the VCO control voltage. When locked, f_VCO/N = f_ref/R, so f_VCO = N times f_ref/R. The channel spacing equals f_comp = f_ref/R. For a 10 MHz reference with R=10, f_comp = 1 MHz, and the VCO can be tuned in 1 MHz steps by changing N. The loop bandwidth (determined by the loop filter) sets the tradeoff between phase noise (narrower is better inside the loop), lock time (wider is faster), and spur rejection.

What is fractional-N synthesis?

Fractional-N synthesis overcomes the integer-N limitation that channel spacing equals the comparison frequency. In integer-N, fine frequency steps require low f_comp, which increases N (the division ratio) and degrades in-band phase noise by 20*log(N). Fractional-N achieves fine frequency resolution while maintaining high f_comp by dynamically switching the divider between N and N+1. A sigma-delta modulator controls the switching pattern to achieve an average division ratio of N plus F/M, where F/M is a fraction. The output frequency is f_out = (N + F/M) times f_comp. With f_comp = 100 MHz and a 24-bit modulator (M = 16 million), the frequency resolution is 100 MHz / 16 million = 6 Hz, while maintaining the low phase noise benefit of high f_comp. The sigma-delta noise shaping pushes quantization noise to high offset frequencies where the loop filter attenuates it.

When should you use DDS vs. PLL?

DDS excels in frequency agility: it can switch frequencies in nanoseconds (limited only by the DAC settling time and digital pipeline delay), while PLLs require microseconds to milliseconds for the loop to settle. DDS also provides phase-continuous frequency switching (no transients), arbitrary frequency resolution (down to microhertz with a 48-bit accumulator), and easy frequency/phase modulation. However, DDS output frequency is limited to about 40 percent of its clock frequency (Nyquist limit with margin for anti-aliasing), and its spurious performance (SFDR of 60 to 80 dBc) is inferior to PLLs (80 to 100 dBc). DDS is ideal for agile waveform generation below 1 GHz, radar chirp synthesis, and arbitrary modulation. PLLs are preferred for higher frequencies (up to 20 GHz and beyond with prescalers), lower phase noise, and cleaner spectral purity. Modern architectures combine both: a DDS clocked by a PLL provides fine-resolution agile output at high frequencies.

Signal Generation

Frequency Synthesizer

/free-kwen-see sin-thuh-sy-zer/

A system generating precise, tunable frequencies from a single reference oscillator. PLL: integer-N (f_out = N × f_ref/R, channel spacing = f_comp) or fractional-N (f_out = (N+F/M) × f_comp, sub-Hz resolution via ΣΔ modulation). DDS: digital phase accumulator + DAC for ns-speed switching but limited to ~40% of clock frequency. Key specs: phase noise, spurious, tuning speed. In every radio, radar, and test instrument.

PLL lock: μs-ms

DDS switch: ns

Frac-N: sub-Hz res

Understanding Frequency Synthesizers

The frequency synthesizer is the heart of every radio system. It converts the single, fixed frequency of a crystal oscillator into any frequency needed by the transceiver, radar waveform generator, or test instrument. The quality of the synthesizer directly determines the radio's spectral purity (phase noise), frequency accuracy (locked to the reference), and agility (how fast it can switch channels or sweep frequencies).

PLL-based synthesis dominates commercial radio because it provides excellent phase noise at high output frequencies with relatively simple circuitry. The PLL acts as a frequency multiplier that preserves the crystal reference's stability while generating the target frequency. Modern fractional-N PLLs with sigma-delta modulators achieve sub-Hz frequency resolution without sacrificing phase noise, enabling direct synthesis of cellular LO frequencies with better than -100 dBc/Hz phase noise at 1 kHz offset.

Synthesizer Equations

PLL frequency synthesis:
f_out = N×f_ref/R

Phase noise in-band:
L_out = L_ref+20logN dB (PLL limited)

Lock time:
t_lock ≈ 10/(2πf_loop)

Channel spacing:
Δf = f_ref/R (integer-N)
Δf = f_ref/R×1/2^F (fractional-N)

Synthesizer Architecture Comparison

Architecture	Step size	PN @1kHz	Lock time	Application
Integer-N	f_ref/R	−90 to −100	50–200 μs	Simple LO
Fractional-N	f_ref/2^F	−100 to −110	10–50 μs	Cellular/5G
DDS	<1 Hz	−110 to −130	<1 μs	Agile radar
DDS+PLL	<1 Hz	−100 to −110	10–50 μs	Wideband
Direct analog	Variable	−120 to −140	<1 μs	Lowest PN

Common Questions

Frequently Asked Questions

How does a PLL synthesizer work?

Reference crystal divided by R produces f_comp. VCO divided by N produces f_VCO/N. PFD compares phases, charge pump + loop filter generate VCO control voltage. When locked: f_VCO = N × f_comp. Channel spacing = f_comp. Loop bandwidth sets phase noise / lock time / spur rejection tradeoff. In-band noise = L_ref + 20log(N).

What is fractional-N?

Overcomes integer-N constraint (spacing = f_comp). ΣΔ modulator alternates divider between N and N+1, achieving average N + F/M. 24-bit ΣΔ at f_comp=100 MHz: 6 Hz resolution while keeping high f_comp for low N and low phase noise. Quantization noise shaped to high offsets where loop filter rejects it. Dominant modern architecture.

DDS vs. PLL?

DDS: ns switching, phase-continuous, μHz resolution, easy modulation. But limited to ~40% of clock, SFDR 60-80 dBc. PLL: higher frequencies (20+ GHz), lower phase noise, cleaner spurs (80-100 dBc), but μs-ms lock time. Hybrid: DDS clocked by PLL gives agile fine-resolution at higher frequencies. DDS for agile waveforms; PLL for clean LOs.

Related Terms

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