Synth Architecture

Frequency Synthesizer Architecture

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A frequency synthesizer generates a stable, tunable output frequency from a fixed reference using PLL, DDS, or combination architectures. Integer-N PLLs provide channel frequencies at multiples of the reference. Fractional-N PLLs allow finer resolution. Direct Digital Synthesis (DDS) provides sub-Hz resolution with fast switching. Modern synthesizers combine PLL and DDS for optimal phase noise, agility, and resolution.
Category: Signal Sources
Related to: Synthesizer, PLL, DDS, VCO, Phase Noise
Units: GHz, dBc/Hz

Understanding Synthesizer Architectures

Frequency synthesizers are at the heart of every modern radio system. The synthesizer determines the channel frequency, switching speed, phase noise, and spurious performance of the entire system.

Synthesizer Types

  • Integer-N PLL: Output = N x f_ref. Simple, good phase noise. Step size = f_ref. Slow switching for fine steps.
  • Fractional-N PLL: Output = (N + F/M) x f_ref. Fine resolution with high reference. Modern sigma-delta types achieve excellent phase noise.
  • DDS + PLL: DDS provides fine resolution and fast switching. PLL cleans up DDS spurs and provides frequency multiplication.
  • Direct analog: Mixing and dividing from multiple oscillators. Lowest phase noise but complex and expensive.
Common Questions

Frequently Asked Questions

What is a frequency synthesizer?

A synthesizer generates stable, tunable frequencies from a fixed reference. Types include integer-N PLL (simple), fractional-N PLL (fine resolution), DDS (sub-Hz resolution, fast), and hybrid combinations for optimal performance.

What determines synthesizer phase noise?

In-band phase noise is set by the reference, divider ratio N (20logN degradation), and PLL IC noise. Out-of-band phase noise is set by the VCO. Lower N ratios (higher reference) give better in-band noise. DDS has flat noise profile.

How fast can a synthesizer switch?

Integer-N PLL: 100 us - 10 ms. Fractional-N PLL: 10-100 us. DDS: < 1 us (essentially instantaneous). Direct analog: < 1 us. Faster switching requires wider loop bandwidth (PLL) or DDS architecture.

Signal Sources

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