Transmission Lines

CPW-to-SIW Transition

Q: How does a CPW-to-SIW current-probe transition actually couple power into the waveguide?

The center strip of the coplanar waveguide is extended past the SIW broadwall edge and tapered into a metal probe that penetrates roughly a quarter of the way into the SIW cavity, near one sidewall. The probe behaves like a monopole launching the vertical electric field of the TE10 mode. Because the CPW mode is quasi-TEM with field concentrated in the slots, and the SIW supports a TE10 mode with a half-sinusoid field across the width, the tapered probe gradually reshapes the field distribution. The probe length sets the imaginary part of the input impedance, while the probe position relative to the sidewall (which controls how much of the half-sine field it samples) sets the real part. Designers tune both to present 50 ohms back to the CPW. Via fences on each side of the probe suppress parallel-plate leakage and confine the field to the intended launch region.

Q: What return loss and bandwidth can a single CPW-to-SIW transition realistically achieve?

A well-optimized current-probe or tapered CPW-to-SIW transition typically delivers better than 15 dB return loss over a 25 to 35 percent fractional bandwidth, with insertion loss of 0.3 to 0.8 dB per transition once dielectric and conductor losses are included. Back-to-back test structures (two transitions plus a length of SIW) commonly show 0.6 to 1.2 dB total. The bandwidth is bounded below by the SIW cutoff frequency of the TE10 mode and above by the onset of the TE20 mode and by higher-order CPW modes; both must be kept outside the band. On a 0.254 mm Rogers RT/duroid 5880 substrate at Ka-band, transitions covering 26 to 40 GHz with better than 18 dB return loss are routinely reported.

Q: Why use a via fence around the CPW launch instead of a solid metal wall?

Substrate integrated waveguide is built entirely in a multilayer PCB or LTCC process, so the sidewalls cannot be solid metal; they are emulated by two rows of plated vias. For the vias to behave like a continuous wall, the via diameter d and pitch p must satisfy d greater than the guide wavelength divided by 5 and p less than 2d, which keeps leakage between adjacent vias below a fraction of a dB. The same rule governs the via fence placed around the CPW probe at the transition: tightly spaced vias short the parallel-plate mode and force current to return through the intended path, preventing surface-wave and substrate-mode loss that would otherwise degrade return loss and radiate.

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Bridging two very different guiding structures, this interconnect launches energy from a planar coplanar waveguide feed into a substrate integrated waveguide realized inside the same PCB or LTCC stack-up. A tapered current probe formed by the CPW center strip penetrates the SIW broadwall near one via sidewall, converting the quasi-TEM CPW field into the half-sinusoid TE₁₀ mode of the waveguide. Surrounding via fences suppress parallel-plate leakage so that a single transition reaches better than 15 dB return loss over a 25 to 35% fractional bandwidth with 0.3 to 0.8 dB insertion loss, making it the workhorse feed for millimeter-wave SIW filters, antennas, and integrated front ends.

Category: Transmission Lines

Return Loss: > 15 dB

Fractional BW: 25 to 35%

Launching a Planar Feed Into Substrate Integrated Waveguide

Substrate integrated waveguide gives designers the low loss and high power handling of a rectangular waveguide while keeping everything inside a flat multilayer board: two copper planes form the broadwalls and two rows of plated vias emulate the sidewalls. The catch is that nothing on a PCB naturally excites the SIW TE₁₀ mode. Active devices, connectors, and microstrip or coplanar circuits all speak in quasi-TEM, so a transition is required to reshape that field into the vertical, half-sinusoid distribution the waveguide wants. The CPW-to-SIW transition solves this for coplanar feeds, which are attractive at millimeter-wave frequencies because they avoid backside vias and present a ground-signal-ground footprint that probes and flip-chip dies mate with directly.

The most common topology is the tapered current probe. The CPW center conductor extends past the SIW edge and narrows into a metal finger that drops into the dielectric near one of the via sidewalls. Because the TE₁₀ field peaks at the waveguide center and vanishes at the walls, the probe samples a fraction of that half-sine profile set by its lateral position, which controls the real part of the input impedance. Probe length controls the reactance. By co-optimizing position and length the designer presents a clean 50 ohm match back to the CPW. A second family, the tapered-slot or antipodal design, instead morphs the CPW slots into the SIW aperture over a smooth taper, trading a longer footprint for wider bandwidth.

Mode Conversion and the Cutoff Constraint

The transition is fundamentally a mode conversion problem. The usable band sits above the TE₁₀ cutoff and below the TE₂₀ onset, exactly as in a hollow waveguide, but the effective width is reduced by the dielectric and by the via-wall offset. Getting the via geometry right is what keeps the SIW behaving like a solid-wall guide rather than a leaky slot array.

Governing Equations

SIW effective width (solid-wall equivalent):
w_eff ≈ w − d² / (0.95 × p)

TE₁₀ cutoff frequency:
f_c = c / (2 × w_eff × √ε_r)

Via fence design rules (low leakage):
d > λ_g / 5 and p < 2 × d

Guide wavelength in the SIW:
λ_g = λ₀ / √(ε_r − (λ₀ / (2 × w_eff))²)

Where w = center-to-center via row spacing, d = via diameter, p = via pitch, ε_r = substrate permittivity, λ₀ = free-space wavelength. Example: w = 4.0 mm, d = 0.5 mm, p = 0.8 mm on ε_r = 2.2 gives w_eff ≈ 3.67 mm and f_c ≈ 27.6 GHz.

Transition Topology Comparison

Transition Type	Typical Return Loss	Fractional BW	Footprint	Insertion Loss	Best Use
CPW current probe	> 15 dB	25 to 35%	Compact (~λ_g/4)	0.3 to 0.8 dB	On-wafer probing, flip-chip
CPW tapered slot	> 18 dB	35 to 50%	Long taper	0.4 to 0.9 dB	Wideband mmWave links
Microstrip taper	> 20 dB	30 to 45%	Medium	0.2 to 0.6 dB	Single-layer SIW boards
GCPW probe	> 15 dB	20 to 30%	Compact	0.4 to 0.9 dB	Thick or lossy substrates
Aperture / slot coupled	> 15 dB	15 to 25%	Multilayer	0.5 to 1.2 dB	Stacked LTCC modules

Common Questions

Frequently Asked Questions

How does a CPW-to-SIW current-probe transition actually couple power into the waveguide?

The CPW center strip extends past the SIW edge and tapers into a probe that penetrates roughly λ_g/4 into the dielectric near one sidewall, launching the vertical E-field of the TE₁₀ mode. Probe length sets the input reactance; the probe's lateral position relative to the sidewall, which determines how much of the half-sine field it samples, sets the resistance. Both are tuned for a 50 ohm match, and a via fence around the probe confines the field and blocks parallel-plate leakage.

What return loss and bandwidth can a single CPW-to-SIW transition realistically achieve?

An optimized current-probe transition delivers better than 15 dB return loss across a 25 to 35% fractional bandwidth, with 0.3 to 0.8 dB insertion loss per transition. Back-to-back structures show 0.6 to 1.2 dB total. The band is bounded by the TE₁₀ cutoff below and the TE₂₀ onset above. On 0.254 mm RT/duroid 5880 at Ka-band, designs covering 26 to 40 GHz with better than 18 dB return loss are routine.

Why use a via fence around the CPW launch instead of a solid metal wall?

SIW lives entirely inside a PCB or LTCC stack, so solid sidewalls are impossible; two rows of plated vias emulate them. To behave like a continuous wall the vias must satisfy d > λ_g/5 and p < 2d, keeping inter-via leakage to a fraction of a dB. The same fence around the CPW probe shorts the parallel-plate mode and forces the return current through the intended path, preventing surface-wave loss and radiation that would wreck the return loss.

Related Terms

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