Transmission Lines

CPW Loss (Design)

Q: Does narrowing the CPW gap reduce or increase loss?

Narrowing the slot gap (G) while keeping the center conductor width (W) fixed concentrates the electric field in the gap and crowds current at the conductor edges, which raises conductor loss because the effective current cross-section shrinks. However, a tighter gap also raises the line impedance and changes the W/(W+2G) ratio, so designers usually trade gap and width together to hold 50 ohms. For lowest conductor loss at a fixed impedance, you want the widest practical center conductor, which means a proportionally wider gap. A common rule is that doubling all linear dimensions (W, G, and substrate thickness) roughly halves conductor loss per unit length, at the cost of a larger footprint and a lower frequency at which higher-order or microstrip-like modes appear. So narrowing the gap to save board space typically increases loss.

Q: Why does CPW conductor loss rise with the square root of frequency?

Conductor loss in CPW is dominated by the skin effect. As frequency rises, current crowds into a surface layer whose thickness, the skin depth, scales as 1/sqrt(f). Thinner conduction means higher surface resistance Rs, which scales as sqrt(f). Because the attenuation contribution is proportional to Rs, conductor loss alpha_c grows as sqrt(f). At W-band (75 to 110 GHz) the skin depth in gold is only about 0.24 microns, so surface roughness and plating quality strongly affect realized loss. Dielectric loss, by contrast, grows linearly with frequency, so above roughly 30 to 60 GHz on a lossy substrate the dielectric term can overtake the conductor term. Radiation loss grows even faster, roughly with the cube of frequency, which is why grounded CPW and mode-suppression vias matter at millimeter-wave.

Q: How much loss does CPW have compared with microstrip at 60 GHz?

On a thin high-resistivity substrate, conventional CPW and microstrip have broadly similar total loss near 60 GHz, often in the range of 0.5 to 1.5 dB/mm depending on substrate and conductor quality. CPW keeps both signal and ground on the top metal, which simplifies shunt and series component mounting and removes the need for through-wafer vias, but its coplanar grounds can support an unwanted parallel-plate or slotline mode and radiate at discontinuities. Grounded CPW with a backside ground and a dense via fence suppresses these modes and is the common millimeter-wave choice. On low-loss substrates such as fused silica or high-resistivity silicon, CPW can reach about 0.3 to 0.6 dB/mm at 60 GHz. The right comparison always depends on substrate loss tangent, metal thickness, and how well parasitic modes are controlled.

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Budgeting and minimizing the attenuation of a coplanar waveguide is what CPW loss design is about. Three mechanisms add in series: conductor loss from skin-effect surface resistance (rising as √f), dielectric loss set by the substrate loss tangent (rising linearly with f), and radiation or parasitic-mode leakage (rising roughly as f³). Because the signal and both grounds sit on the same top metal, gap (G) and center-conductor width (W) can be scaled together to hold 50 Ω while widening the conductor to cut edge current crowding. Typical realized loss runs 0.05 to 0.3 dB/mm below 20 GHz and 0.5 to 1.5 dB/mm at W-band, where a 0.24 µm gold skin depth makes surface roughness and plating quality dominate the budget.

Category: Transmission Lines

Typical Loss: 0.05 to 1.5 dB/mm

Conductor α: ∝ √f

Where CPW Attenuation Comes From

Coplanar waveguide places the signal conductor and its two return grounds on a single metal layer, separated by narrow slots. That geometry makes it easy to mount series and shunt components and to probe on-wafer, but it also means the total attenuation constant is the sum of three distinct physical processes. The conductor term comes from finite metal conductivity and the skin effect, which forces current into a thin surface layer and crowds it at the slot edges where the field is most intense. The dielectric term comes from the imaginary part of the substrate permittivity, captured by the loss tangent. The radiation and leakage term comes from energy coupling into substrate modes, the parasitic coupled-slotline mode between the two grounds, or free-space radiation at bends and transitions.

For most RF boards below about 20 GHz, conductor loss dominates and the design lever is geometry: a wider center conductor at a fixed 50 Ω impedance spreads the current and lowers skin-depth-limited resistance. As frequency climbs into the millimeter-wave bands, two things change. Dielectric loss, which grows linearly with frequency, can overtake conductor loss on a lossy substrate, so material choice (alumina, fused silica, high-resistivity silicon, or quartz) becomes the dominant decision. And radiation, which grows much faster, forces designers toward grounded CPW with a backside ground plane stitched by a dense fence of vias to short out the parallel-plate and slotline modes.

Practical loss design therefore proceeds as a budget. You start from a target insertion loss for the line length, allocate it across the three mechanisms, then choose conductor thickness (at least three to five skin depths), slot and conductor width, substrate, and mode-suppression structure to hit it. Surface roughness deserves explicit attention: at W-band the gold skin depth is only about a quarter micron, so an RMS roughness of even 0.1 to 0.3 µm can multiply conductor loss by 1.5 to 2 times relative to a perfectly smooth surface.

Governing Loss Equations

Total attenuation constant:
α_total = α_c + α_d + α_r (Np/m or, ×8.686, dB/m)

Conductor (skin-effect) loss:
α_c ≈ R_s / (Z₀ × effective width), R_s = √(π f μ / σ) ∝ √f

Dielectric loss:
α_d = (π / λ₀) × (ε_r / √ε_eff) × ((ε_eff − 1)/(ε_r − 1)) × tanδ ∝ f

Skin depth:
δ_s = 1 / √(π f μ σ)

Where R_s = surface resistance, Z₀ = line impedance, σ = conductivity, μ = permeability, ε_eff = effective permittivity, tanδ = loss tangent. Example: gold (σ ≈ 4.1×10⁷ S/m) at 60 GHz gives δ_s ≈ 0.31 µm and R_s ≈ 0.064 Ω/sq.

Loss Mechanism Comparison

Mechanism	Frequency scaling	Primary driver	Design lever	Dominant when
Conductor (α_c)	∝ √f	Surface resistance, edge crowding, roughness	Wider conductor, smoother/thicker plating	< ~20 GHz, low-loss substrate
Dielectric (α_d)	∝ f	Substrate loss tangent tanδ	Lower-tanδ material (quartz, fused silica)	mmWave on FR-4 or standard ceramics
Radiation / leakage (α_r)	∝ ~f³	Slotline mode, parallel-plate mode, bends	Grounded CPW, via fence, air-bridges	High f, thick substrate, discontinuities
Total (α_total)	Sum of above	Combined budget	Co-optimize geometry + material + grounding	Always evaluated end-to-end

Common Questions

Frequently Asked Questions

Does narrowing the CPW gap reduce or increase loss?

Narrowing the slot gap while holding the center width fixed crowds current at the conductor edges and raises conductor loss because the effective conduction cross-section shrinks. To keep 50 Ω, gap and width are scaled together; the lowest conductor loss comes from the widest practical conductor with a proportionally wider gap. Doubling all linear dimensions roughly halves conductor loss per unit length, at the cost of footprint and earlier onset of parasitic modes. So shrinking the gap to save space usually increases loss.

Why does CPW conductor loss rise with the square root of frequency?

Conductor loss is set by the skin effect: skin depth scales as 1/√f, so surface resistance R_s scales as √f, and α_c ∝ R_s follows. Dielectric loss instead grows linearly with f, and radiation grows roughly as f³, so above about 30 to 60 GHz on a lossy substrate the dielectric and radiation terms can overtake the conductor term. At W-band the gold skin depth is only ~0.24 µm, making roughness and plating quality decisive.

How much loss does CPW have compared with microstrip at 60 GHz?

On a thin, high-resistivity substrate, conventional CPW and microstrip have broadly similar total loss near 60 GHz, often 0.5 to 1.5 dB/mm depending on substrate and metal quality. CPW eases component mounting and on-wafer probing with no through-vias, but its coplanar grounds can support a parasitic slotline mode and radiate at discontinuities, so grounded CPW with a via fence is the usual mmWave choice. On fused silica or high-resistivity silicon, CPW can reach about 0.3 to 0.6 dB/mm at 60 GHz.

Related Terms

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