Transmission Lines

CPW Impedance (Design)

Q: What strip width and gap give a 50 ohm CPW on alumina?

On a 0.635 mm thick alumina substrate (relative permittivity 9.8) a conductor-backed coplanar waveguide reaches about 50 ohms with a center strip near 0.5 mm and a gap of roughly 0.25 mm, giving a width-to-gap ratio close to 2. Because CPW impedance is governed by the ratio of strip width to slot width rather than absolute dimensions, the same 50 ohm result can be obtained with a 0.25 mm strip and a 0.125 mm gap, or a 1.0 mm strip and a 0.5 mm gap, as long as the ratio is preserved and the line stays well below the substrate-mode cutoff. Designers usually run a 2D field solver to set the final dimensions because finite metal thickness, the ground-plane spacing, and a backing conductor all shift the result by a few ohms.

Q: How does CPW impedance change when you add a backside ground plane?

Adding a backside ground plane turns ordinary CPW into conductor-backed coplanar waveguide. The lower conductor adds a parallel-plate capacitance path, so for the same top-side geometry the characteristic impedance drops. To return to 50 ohms you must either narrow the gaps, widen the center strip, or use a thicker substrate so the backside ground is electrically farther away. As a rule of thumb, when the substrate thickness is greater than about twice the ground-to-ground spacing the backing conductor has little effect and the line behaves like true CPW; when it is thinner the line trends toward microstrip behavior and the effective permittivity rises.

Q: Why is CPW impedance nearly independent of substrate thickness?

In a true coplanar waveguide the signal strip and both return-current ground planes sit on the same surface, so the dominant fields are concentrated in the gaps between them. The characteristic impedance is set by the ratio of strip width to slot width through a conformal mapping that yields a ratio of complete elliptic integrals, K(k)/K(k prime). Because that mapping depends only on the in-plane ratios and not on how thick the dielectric is, you can scale all the top-side dimensions up or down together and keep the same impedance. This lets you trade conductor loss against size, or match a connector pad, without re-tuning impedance, which is the main practical advantage of CPW over microstrip.

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Setting a target characteristic impedance for a coplanar waveguide comes down to choosing the center-strip width W and the two slots S that separate it from the surrounding ground planes. Because the dominant fields live in those gaps, the impedance is governed by the width-to-gap ratio W/(W+2S) through a conformal mapping rather than by absolute size, so the entire cross-section can be scaled while holding a fixed value such as 50 Ω. That property gives the designer a degree of freedom that microstrip lacks, since microstrip impedance is locked to the substrate thickness. On alumina (ε_r = 9.8) a 50 Ω line typically uses a W/S ratio near 2, with the exact effective permittivity falling between 1 and (ε_r+1)/2 because half the field returns through air.

Category: Transmission Lines

Typical target: 50 Ω (W/S ≈ 2 on alumina)

Range: 20 to 120 Ω

Setting CPW Impedance With Strip and Gap Geometry

Coplanar waveguide places the signal conductor and both return-current ground planes on the same face of the dielectric, with the electric field crossing the two slots on either side of the center strip. Because those slots dominate the stored energy, the line capacitance and therefore the characteristic impedance depend almost entirely on the in-plane ratio of strip width to slot width. A wide strip with narrow gaps stores more capacitance and produces a low impedance; a narrow strip with wide gaps does the opposite. Practical CPW designs span roughly 20 to 120 Ω, with 50 Ω the near-universal target for connectorized test fixtures and monolithic circuits.

The closed-form solution uses conformal mapping, which transforms the slotted cross-section into a parallel-plate capacitor and yields the impedance as a ratio of complete elliptic integrals K(k)/K(k′). The modulus k is set purely by the geometry, k = a/b where a is the half-strip width and b is the half-spacing to the outer ground edge. Because k carries no thickness term, scaling W and S together leaves the impedance unchanged. The substrate enters only through the effective permittivity, which for a thick substrate approaches the average of the dielectric and air, (ε_r+1)/2, since the field divides between the two media.

Real designs depart from the ideal in three ways. Finite metal thickness lowers impedance by a few ohms and is corrected with an effective-gap adjustment. Adding a backside conductor creates conductor-backed CPW, which introduces a parallel-plate path that drops impedance and raises effective permittivity. And the finite ground-plane width sets where parasitic slotline and parallel-plate modes appear, so the ground-to-ground spacing must stay below about a tenth of a guided wavelength to keep the line single-moded.

Conformal-Mapping Design Equations

Characteristic impedance (ideal CPW):
Z₀ = (30π / √ε_eff) × K(k′) / K(k) Ω

Geometry modulus:
k = a / b = W / (W + 2S) and k′ = √(1 − k²)

Effective permittivity (thick substrate):
ε_eff ≈ (ε_r + 1) / 2

Where W = center-strip width, S = slot width, a = W/2, b = W/2 + S, K = complete elliptic integral of the first kind, ε_r = substrate relative permittivity. Example: on alumina (ε_r = 9.8, ε_eff ≈ 5.4) a W/S ratio ≈ 2 gives Z₀ ≈ 50 Ω.

50 Ohm CPW Geometry by Substrate

Substrate	ε_r	ε_eff	W/S for 50 Ω	Example W / S	Notes
Alumina	9.8	~5.4	~2.0	0.50 / 0.25 mm	Thin-film MMIC carriers
GaAs	12.9	~7.0	~2.3	50 / 25 μm	On-wafer probe lines
Fused silica	3.8	~2.4	~1.2	0.30 / 0.25 mm	Low-loss, mmWave
RO4350B	3.66	~2.3	~1.1	1.0 / 0.9 mm	PCB-level CPW
Silicon (CB-CPW)	11.9	~6.5	~2.6	40 / 15 μm	Backing ground lowers Z₀

Common Questions

Frequently Asked Questions

What strip width and gap give a 50 ohm CPW on alumina?

On 0.635 mm alumina (ε_r = 9.8) a 50 Ω line lands near a 0.50 mm strip with 0.25 mm gaps, a W/S ratio close to 2. Since impedance follows the ratio, not absolute size, a 0.25 mm strip with 0.125 mm gaps gives the same result. Finite metal thickness and any backing conductor shift it a few ohms, so confirm dimensions in a 2D field solver.

How does CPW impedance change when you add a backside ground plane?

A backside ground turns the line into conductor-backed CPW and adds a parallel-plate capacitance path, so for the same top geometry Z₀ drops. To recover 50 Ω you narrow the slots, widen the strip, or thicken the substrate. When the substrate is thicker than about twice the ground-to-ground spacing the backing has little effect; thinner, and the line trends toward microstrip behavior with higher ε_eff.

Why is CPW impedance nearly independent of substrate thickness?

With the strip and both grounds coplanar, the fields concentrate in the gaps, and the impedance follows the ratio of strip width to slot width through the conformal-mapping factor K(k)/K(k′). That mapping uses only in-plane ratios, so scaling all top dimensions together holds Z₀ fixed. This lets you trade conductor loss against size or match a connector pad without re-tuning impedance, which microstrip cannot do.

Related Terms

← CPW Ground Width CPW Loss (Design) →

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