CPW Design Equations
How Conformal Mapping Solves the Coplanar Geometry
A coplanar waveguide places the signal conductor and both return grounds on the same surface of the substrate, separated by two narrow slots. Solving the field problem in closed form would be intractable in the physical plane, so the standard treatment by Wen, Gupta, and later Simons uses conformal mapping to transform the three-conductor cross section into a parallel-plate capacitor. The mapping turns the in-plane dimensions into a single geometric modulus k = a/b, where a = S/2 and b = S/2 + W, so that k = S/(S + 2W). Every impedance and capacitance result then reduces to the ratio of complete elliptic integrals of the first kind, K(k) over K(k'), with the complementary modulus k' = √(1 − k2).
The elegance is that impedance depends only on the ratio of widths, not their absolute scale, so a line can be shrunk or grown without changing Z0 as long as S and W track together. That property is why CPW dominates on-wafer test structures: a 50 Ω pad pitch can be set by the probe and the line still matches. The effective permittivity comes from averaging the air and dielectric half-spaces, giving εeff ≈ (εr + 1)/2 in the quasi-static limit. On alumina that is about 5.45 and on GaAs about 6.95, and because the controlling field lives in the surface gaps rather than under the conductor, dispersion stays small even at millimeter-wave frequencies.
The Governing Equations
k = S / (S + 2W), k' = √(1 − k2)
Effective dielectric constant (thick substrate):
εeff ≈ (εr + 1) / 2
Characteristic impedance:
Z0 = 30π / √εeff × K(k') / K(k) Ω
Elliptic-integral ratio (Hilberg, 0 ≤ k ≤ 0.707):
K(k)/K(k') = π / ln[ 2 (1 + √k') / (1 − √k') ]
Where S = center-conductor width, W = slot gap to each ground, εr = substrate relative permittivity. Example: on alumina (εr = 9.9) with S = 50 μm and W = 30 μm, k ≈ 0.45 and εeff ≈ 5.45 give Z0 ≈ 50 Ω.
50-Ohm Geometry Across Common Substrates
| Substrate | εr | εeff ≈ | S / W for 50 Ω | Modulus k | Typical use |
|---|---|---|---|---|---|
| Alumina | 9.9 | 5.45 | 50 / 30 μm | 0.45 | Thin-film hybrids |
| GaAs | 12.9 | 6.95 | 40 / 26 μm | 0.43 | MMIC interconnect |
| Silicon | 11.9 | 6.45 | 45 / 30 μm | 0.43 | RFIC, SiGe |
| Fused silica | 3.8 | 2.40 | 40 / 16 μm | 0.56 | mmWave probe pads |
| RT/duroid 5880 | 2.2 | 1.60 | 1.5 / 0.5 mm | 0.60 | PCB uniplanar |
Frequently Asked Questions
How do you compute the impedance ratio k for a coplanar waveguide?
The modulus is k = a/b with a = S/2 and b = S/2 + W, so k = S/(S + 2W). Impedance follows from K(k)/K(k') with k' = √(1 − k2). For k from 0 to 0.707 the Hilberg form K(k)/K(k') = π / ln[2(1 + √k')/(1 − √k')] holds; the reciprocal branch covers 0.707 to 1, keeping error under about 0.1%.
Why does the effective permittivity of CPW stay close to (εr + 1)/2 over frequency?
Roughly half the field sits in air above the slots and half in the substrate, so εeff ≈ (εr + 1)/2: about 5.45 on alumina, 6.95 on GaAs. Because the field is set by the in-plane S and W rather than substrate thickness, CPW disperses far less than microstrip, often under a few percent up to 40 GHz, which suits millimeter-wave MMIC and on-wafer probing.
How does adding a backside ground plane change the CPW equations?
A conductor-backed CPW adds a second ratio K(k3)/K(k3') with k3 = tanh(πS/4h)/tanh(π(S + 2W)/4h), h being substrate thickness. The permittivity becomes εeff = (1 + εrq)/(1 + q) with a filling factor q. As h shrinks the line behaves like microstrip, εeff climbs toward εr, and 50 Ω needs wider gaps.