What is the typical bias sequence for a GaN MMIC to avoid damage?
GaN Bias Sequencing
Depletion-mode GaN HEMTs are normally-on devices: with Vgs = 0V, the channel is fully open and the transistor draws maximum current (Idss). This is fundamentally different from silicon MOSFETs and enhancement-mode GaAs devices which are normally-off. The depletion-mode behavior creates a potential damage scenario if the drain voltage is applied before the gate is negatively biased.
The bias sequence provides a controlled path to the operating point: first, the negative gate voltage pinches off the channel (zero drain current). Then, the drain voltage is applied into a high-impedance (pinched-off) channel, and no current flows. Finally, the gate voltage is adjusted to the desired operating bias point (quiescent current = 10-30% of Idss for Class AB). The device ramps up smoothly to its operating current without any current spikes.
Bias sequencing circuits use dedicated power supply controllers (such as Texas Instruments LM3880, LM3881, or custom circuits) that generate the correct voltage timing. The gate supply must reach its negative target before the drain supply begins ramping. A delay of 1-10 ms between gate and drain application is typical.
Frequently Asked Questions
What happens if I get the sequence wrong?
Applying Vds before Vgs: the transistor draws maximum current (Idss), potentially causing thermal damage or electromigration failure. Power dissipation = Vds × Idss can be 10-50× the normal operating power. Even brief exposure (milliseconds) can degrade or destroy the device.
Do all GaN devices need sequencing?
Depletion-mode GaN HEMTs (the majority): yes, always gate-first. Enhancement-mode GaN (E-mode, normally-off): no sequencing needed because the channel is off with Vgs = 0V. E-mode GaN is used in some power switching applications but is less common in RF.
How do I implement sequencing?
Use a sequencing IC (TI LM3880) to control the enable pins of the gate and drain power supplies. Gate supply enables first, stabilizes, then drain supply enables. On power-down, the drain supply disable assertion triggers before the gate supply. Add a monitor circuit that shuts down the drain if the gate supply fails.