Amplifier Selection and Design LNA Selection and Design Informational

What is the role of source inductance in LNA noise matching?

A small inductor (0.1-0.5 nH) in the FET source (or BJT emitter) transforms the transistor's optimum noise impedance Γopt to move it closer to the conjugate match point on the Smith Chart. Without source inductance, Γopt and S11* are at different locations, forcing the designer to choose between noise match (NF = NFmin, gain < MAG) or power match (gain = MAG, NF > NFmin). Source inductance degenerates the transistor, rotating Γopt toward the real axis and toward S11*, enabling simultaneous noise and power matching with only 0.1-0.3 dB NF penalty. This is the most important technique in practical LNA design.
Category: Amplifier Selection and Design
Updated: April 2026
Product Tie-In: LNAs, Transistors, Bias Tees

Source Degeneration for LNA

In a common-source (or common-emitter) LNA without degeneration, the input impedance is predominantly capacitive (gate-source capacitance) while the optimum noise impedance has a significant real part. This means the matching network cannot simultaneously present the optimum noise impedance and the conjugate match impedance to the transistor, forcing a compromise between NF and gain.

ParameterLNADriverPower Amplifier
Noise Figure0.3-2.0 dB3-8 dB5-15 dB (not specified)
Gain10-25 dB10-20 dB8-15 dB
P1dB-10 to +10 dBm+15 to +25 dBm+30 to +50 dBm
OIP3+5 to +25 dBm+25 to +40 dBm+40 to +55 dBm
DC Power10-100 mW0.5-5 W5-500 W
  • Performance verification: confirm specifications against the application requirements before finalizing the design
  • Environmental factors: temperature range, humidity, and vibration affect long-term reliability and parameter drift
  • Cost vs. performance: evaluate whether the application demands premium components or standard commercial grades
  • Interface compatibility: verify impedance, connector type, and mechanical form factor match the system architecture
  • Margin allocation: include sufficient design margin to account for manufacturing tolerances and aging effects
Common Questions

Frequently Asked Questions

How much inductance do I need?

Typically 0.1-0.5 nH at 1-5 GHz. The required value depends on the transistor's gm and Cgs. A rough estimate: Ls ≈ 50Ω × Cgs/gm. At higher frequencies, the required Ls decreases. The value is optimized by simulation using the transistor's noise parameters.

How do I implement sub-nH inductance?

Short wire bonds (0.5-1 nH/mm), via holes through a ground plane (0.1-0.3 nH per via), or a short microstrip trace to ground. In MMIC designs, the source via inductance itself provides the degeneration. In hybrid designs, bond wire length controls the inductance.

Does source degeneration affect linearity?

Yes, positively. Source degeneration improves IIP3 by 3-6 dB because the feedback linearizes the transconductance. This is a secondary benefit of the technique. The improved linearity comes at the cost of reduced gain, which is the same tradeoff as any negative feedback.

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