Amplifier Selection and Design LNA Selection and Design Informational

How do I bias an RF transistor for optimal noise figure versus optimal gain?

An RF transistor has different optimum source impedances for minimum noise figure (Γopt) and maximum gain (Γms). Biasing for minimum noise requires presenting Γopt to the transistor input, which typically results in a deliberate input mismatch and 1-3 dB gain reduction from the maximum available gain (MAG). Biasing for maximum gain requires conjugate matching (Γms), which yields higher noise figure (typically 1-3 dB above NFmin). The design compromise involves plotting noise circles and gain circles on the Smith Chart and selecting a source impedance that balances both specifications.
Category: Amplifier Selection and Design
Updated: April 2026
Product Tie-In: LNAs, Transistors, Bias Tees

Noise vs Gain Optimization

Every transistor has two distinct operating regimes: the minimum noise figure condition and the maximum available gain condition. These two optimum points almost never coincide because the physical mechanisms that control noise (channel electron velocity fluctuations, gate resistance) and gain (transconductance, output impedance) depend on different aspects of the current distribution within the device.

At the minimum noise bias point, the transistor operates at relatively low drain current (typically 10-30% of Idss for FETs) where the channel is lightly populated with electrons and the noise generation is minimized. At the maximum gain bias point, the drain current is higher (30-50% of Idss) to maximize transconductance.

For LNA design, the bias point and source impedance are chosen to minimize noise figure (or to achieve a target NF with some gain). For driver and gain block design, the bias point is chosen to maximize gain or maximize linearity (IIP3). The two optimization goals produce fundamentally different circuit designs.

Common Questions

Frequently Asked Questions

How much gain do I sacrifice for minimum noise?

Typically 1-3 dB below the MAG at the same frequency. This is called the associated gain. A transistor with 20 dB MAG might provide 17-19 dB gain when noise-matched. The gain sacrifice depends on how far Γopt is from the conjugate match point.

What bias current gives minimum noise?

For GaAs pHEMT: 15-20% of Idss (typically 5-15 mA). For SiGe HBT: 1-5 mA collector current. For GaN HEMT: 5-15% of Idss. The exact optimum depends on the specific device geometry and frequency. The data sheet noise parameters (NFmin, Γopt, Rn) are specified at the recommended noise bias point.

Can I achieve both low noise and high gain?

Use inductive source degeneration (a small inductor in the FET source or BJT emitter). This technique moves Γopt closer to the conjugate match point without significantly degrading NFmin. With 0.2-0.5 nH source inductance, simultaneous noise and input match within 0.3 dB of NFmin is often achievable.

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